1. Lab 05
Sen Ma

2. What is a Register ?
“In computer architecture, a register is a small amount of storage available as part of a CPU. ”
--Wikipedia

3. What is Register ?
“In computer architecture, a register is a small amount of storage available as part of a CPU. ”
--Wikipedia
Data in the Random-access memory (RAM)

4. What is Register ?
“In computer architecture, a register is a small amount of storage available as part of a CPU. ”
--Wikipedia
Data in the Random-access memory (RAM)
Registers are stored in a structure called a register file which impalement by using RAM.

5. Assume we have 10 registers.
What is Register ?
Reg_File
Register File’s name R0
0x0000 R1
0x0001 R2 R3 R4 R5 R6 R7 R8 R9
Assume we have 10 registers.
R0 ~ R9
Each register has 16bits.
Another assumption
R0 = 0 and R1 = 1 (forever)

6. Oh Yeah, we have registers! We can design our own instructions
What is Register ?
Reg_File
Oh Yeah, we have registers! R0
0x0000 R1
0x0001 R2 R3 R4 R5 R6 R7 R8 R9
We can design our own instructions
How about this:
R2 = R0 + R1

7. Oh Yeah, we have registers! We can design our own instructions
What is Register ?
Reg_File
Oh Yeah, we have registers! R0
0x0000 R1
0x0001 R2 R3 R4 R5 R6 R7 R8 R9
We can design our own instructions
How about this:
R2 = R0 + R1
R2 = R0 + R1

8. Oh Yeah, we have registers! We can design our own instructions
What is Register ?
Reg_File
Oh Yeah, we have registers! R0
0x0000 R1
0x0001 R2 R3 R4 R5 R6 R7 R8 R9
We can design our own instructions
How about this:
R2 = R0 + R1
R2 = R0 + R1

9. What is Register ? Reg_File Oh Yeah, we have registers!
0x0000 R1
0x0001 R2 R3 R4 R5 R6 R7 R8 R9
We can design our own instructions
How about this:
R2 = R0 + R1
R2 = R0 + R1
We have already know the assembly language:
R2 = R0 + R1
add R2, R0, R1

10. What is Register ? Reg_File One more! add R3, R1, R2 R0 0x0000 R1

11. What is Register ? Reg_File One more! add R3, R1, R2 R0 0x0000 R1

12. You can think about the Reg_File is an Array.
What is Register ?
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9
Behind the scene:
You can think about the Reg_File is an Array.
When you read from or write in the register, it is same operation on an array which you have already know.

13. 1 step, Read R1: Reg_File[1]
What is Register ?
Register File’s name
(array’s name)
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9
Same Example:
add R3, R1, R2
1 step, Read R1: Reg_File[1]

14. 1 step, Read R1: Reg_File[1] 2 step, Read R2: Reg_File[2]
What is Register ?
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9
Same Example:
add R3, R1, R2
1 step, Read R1: Reg_File[1]
2 step, Read R2: Reg_File[2]

15. What is Register ? Reg_File Same Example: add R3, R1, R2
1 step, Read R1: Reg_File[1]
2 step, Read R2: Reg_File[2]
3 step Add Reg_File[1] + Reg_File[2]

16. What is Register ? Reg_File Same Example: add R3, R1, R2
1 step, Read R1: Reg_File[1]
2 step, Read R2: Reg_File[2]
3 step Add Reg_File[1] + Reg_File[2]
4 step, Write R3:
Reg_File[3] = Reg_File[1] + Reg_File[2]

17. Define an array in VHDL:
Register in VHDL
Define an array in VHDL:
type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9

18. Define an array in VHDL:
Register in VHDL
Define an array in VHDL:
type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);
Reg_File
Define a type named “ram_type” which is a array with 16 item. Each item is a 16bits vector R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9

19. Register in VHDL Define an array in VHDL:
type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);
signal Reg_File : ram_type;
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9
Using the “ram_type” to define a signal named “Reg_File”.

20. Define an array in VHDL: Reg_File(3) <= Reg_File(1) + Reg_File(2);
Register in VHDL
Define an array in VHDL:
type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);
signal Reg_File : ram_type;
Reg_File R0
0x0000 R1
0x0001 R2 R3
0x0002 R4 R5 R6 R7 R8 R9
Same Example:
add R3, R1, R2
Reg_File(3) <= Reg_File(1) + Reg_File(2);

21. Register
clk
clear
A_addr
A_data
load
b_addr
c_addr
b_data
c_data

22. Register Entity Register is port(
clk: in std_logic; -- positive edge triggered clock
clear: in std_logic; -- asynchronous reset
a_addr: in std_logic_vector( 3 downto 0); -- input data port
a_data: in std_logic_vector(15 downto 0); -- register select for input a
load: in std_logic; -- load enable
b_addr: in std_logic_vector( 3 downto 0); -- register select for output b
c_addr: in std_logic_vector( 3 downto 0); -- register select for output c
b_data: out std_logic_vector(15 downto 0); -- first output data port
c_data: out std_logic_vector(15 downto 0) -- second output data port );
End Register;

23. Register Requirements: Create a register file.
It should have 16 registers, each being sixteen bits wide.
When the load signal is asserted, a rising edge on clk cause the data on a_data to be stored in the register identified by a_addr.
If the load signal is not asserted, a rising clock edge has no effect.
The data on b_data should be the contents of the register identified by b_addr.
The data on c_data should be the contents of the register identified by c_addr.
Register 0 always contains the value 0. Writing to register 0 is ignored.
Register 1 always contains the value 1. Writing to register 1 is ignored.
When the clear signal is 0, all registers (other than register 1) are reset to 0. Note that this is asynchronous.
Follow the instruction on page 129~130 in Xilinx XST User Guide, reference the example code to implement your own register file.