1. Background: VLSI Courses at Lafayette  ECE 425 - VLSI Circuit Design  Original form: “tall thin designer”  VLSI Processing  CMOS Transistor Characteristics  Parasitic Effects  Custom Layout  Standard-Cell ASICs (Application-Specific Integrated Circuits)  ASIC Design using Hardware Description Languages (HDLs) and CAD Tools  Student design project: “Tiny Chip”  Complete 2.2mm X 2.2mm chip  Fabrication by MOSIS (MOS implementation Service) Educational Program  ECE 426 VLSI System Design  Follow-on to ECE 425  More coverage of HDL-based System Design  Testing of fabricated MOSIS chips Extending ECE 425  New focus on Data Conversion  Digital / Analog Conversion  Comparators  Analog / Digital Conversion  Continued focus on Design  Basic cell analysis and layout  ASIC-style HDL-based design  Full chip design (mixed analog & digital) New Design Projects  D/A Converter  Voltage Scaling design  Hierarchical Layout  A/D Converter  Successive Approximation circuit: designed using HDL / standard cells  D/A Converter used as building block  Uses dynamic analog comparator supplied by instructor  Assembled to complete chip Introduction and Overview Motivation - The Digital Paradox  Digital VLSI chips & applications are pervasive in:  Computer Systems  Telecommunications  Consumer Electronics  Automotive Electronics  BUT analog concerns more important than ever!  Must connect digital chips to an analog world  Many chips now combine analog and digital circuits  Designers must consider analog effects in digital circuits  Bottom Line: Undergraduate VLSI students need exposure to both analog and digital concerns Objectives  Add analog to “broaden” a digital course  Teach concepts as extension of digital analysis and design methods  Focus on data conversion - useful to both analog and digital designers  Maintain strong digital design focus  Lay foundation for further study in analog

2. Mixed-Signal Design Activities Voltage-Scaling D/A Converter Comparator Design (provided by instructors) Successive Approximation A/D Converter Comparator Clock Generator Logic

3. Results and Conclusions Final Chip Layout Fabrication & Testing Results - Fall 2001  15 students completed 8 student chip designs  7 submitted for fabrication to MOSIS  7 chips worked as desgined Conclusions  Successfully integrated analog concerns in previously “all-digital” course  Students created working mixed signal (A/D) chips Future Work  Additional analog coverage  Better integration of testing and design-for test More Information Available at: http://foghorn.cadlab.lafayette.edu/ece425