1. Chapter 6 Introduction to Digital Electronics
Microelectronic Circuit Design
Richard C. Jaeger Travis N. Blalock
Microelectronic Circuit Design
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2. Microelectronic Circuit Design
Chapter Goals
Introduce binary digital logic concepts
Explore the voltage transfer characteristics of ideal and nonideal inverters
Define logic levels and logic states of logic gates
Introduce the concept of noise margin
Present measures of dynamic performance of logic devices
Review of Boolean algebra
Investigate simple transistor, diode, and diode-transistor implementations of the inverter and other logic circuits
Explore basic design techniques of logic circuits
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3. Brief History of Digital Electronics
Digital electronics can be found in many applications in the form of microprocessors, microcontrollers, PCs, DSPs, and an uncountable number of other systems.
The design of digital circuits has progressed from resistor-transistor logic (RTL) and diode-transistor logic (DTL) to transistor-transistor logic (TTL) and emitter-coupled logic (ECL) to complementary MOS (CMOS)
The density and number of transistors in microprocessors has increased from 2300 in the bit 4004 microprocessor to 25 million in the more recent IA-64 chip and it is projected to reach over one billion transistors by 2010
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4. Microelectronic Circuit Design
Ideal Logic Gates
Binary logic gates are the most common style of digital logic
The output will consist of either a 0 (low) or a 1 (high)
The most basic digital building block is the inverter
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5. Microelectronic Circuit Design
The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol
V+ and V- are the supply rails, and VH and VL describe the high and low logic levels at the output
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6. Logic Level Definitions
An inverter operating with power supplies at V+ and 0 V can be implemented using a switch with a resistive load
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7. Logic Voltage Level Definitions
VL – The nominal voltage corresponding to a low-logic
state at the input of a logic gate for vi = VH
VH – The nominal voltage corresponding to a high-logic
state at the output of a logic gate for vi = VL
VIL – The maximum input voltage that will be recognized
as a low input logic level
VIH – The minimum input voltage that will be recognized
as a high input logic level
VOH – The output voltage corresponding to an input
voltage of VIL
VOL – The output voltage corresponding to an input
voltage of VIH
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8. Logic Voltage Level Definitions (cont.)
Note that for the VTC of the nonideal inverter, there is now an undefined logic state
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9. Microelectronic Circuit Design
Noise Margins
Noise margins represent “safety margins” that prevent the circuit from producing erroneous outputs in the presence of noisy inputs
Noise margins are defined for low and high input levels using the following equations:
NML = VIL – VOL
NMH = VOH – VIH
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10. Microelectronic Circuit Design
Noise Margins (cont.)
Graphical representation of where noise margins are defined
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11. Logic Gate Design Goals
An ideal logic gate is highly nonlinear that attempts to quantize the input signal to two discrete states, but in an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins
The input should produce a well-defined output, and changes at the output should have no effect on the input
Voltage levels of the output of one gate should be compatible with the input levels of a proceeding gate
The gate should have sufficient fan-out and fan-in capabilities
The gate should consume minimal power (and area for ICs) and still operate under the design specifications
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12. Dynamic Response of Logic Gates
An important figure of merit to describe logic gates is their response in the time domain
The rise and fall times, tf and tr, are measured at the 10% and 90% points on the transitions between the two states as shown by the following expressions:
V10% = VL + 0.1ΔV
V90% = VL + 0.9ΔV = VH – 0.1ΔV
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13. Microelectronic Circuit Design
Propagation Delay
Propagation delay describes the amount of time between a change at the 50% point input to cause a change at the 50% point of the output described by the following:
The high-to-low prop delay, τPHL, and the low-to-high prop delay, τPLH, are usually not equal, but can be described as an average value:
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14. Dynamic Response of Logic Gates
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15. Microelectronic Circuit Design
Power Delay Product
The power-delay product (PDP) is use as a metric to describe the amount of energy required to perform a basic logic operation and is given by the following equation when P is the average power dissipated be the logic gate:
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16. Review of Boolean AlgebraZ 1 A B Z 1 A B Z 1 A B Z 1 A B Z 1
NOT
Truth Table OR
Truth Table
AND
Truth Table
NOR
Truth Table
NAND
Truth Table
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17. Logic Gate Symbols and Boolean Expressions
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18. Microelectronic Circuit Design
Boolean Identities
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19. Microelectronic Circuit Design
Combinational Logic
Combinational logic forms Boolean functions of the input variables. The outputs at any time, t, are a function of only the inputs at time t. The variables are assumed to be binary.
y1 = f1(a, b, c, d)
y2 = f2(a, b, c, d)
y3 = f3(a, b, c, d)
y4 = f4(a, b, c, d)
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20. Microelectronic Circuit Design
Logic Gates
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21. Microelectronic Circuit Design
Notations
+ denotes logical "or"
. denotes logical "and"
^ denotes exclusive or
 denotes "exclusive or"
' denotes logical negation
overbar denotes logical negation
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22. Microelectronic Circuit Design
Boolean Algebra
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23. Representation of Combinational Logic
Common representations of combinational logic:
Truth Table
Boolean Equations
sum = a'b + ab' = a  b
c_out = a . b
Binary Decision Diagrams
Circuit Schematic
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24. Simplification of Boolean Expressions
A SOP expression has a direct hardware implementation as a two-level And-Or logic circuit.
The cost of hardware implementing a Boolean expression is related to the number of terms in the expression and to the number of literals in a term.
Although a Boolean expression can always be expressed in a canonical form, with every cube containing every literal (in complemented or uncomplemented form), such descriptions usually have more efficient descriptions. In practice, minimization is important.
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25. Simplification (cont.)
A Boolean expression in SOP form is said to be minimal if it contains a minimal number of product terms and literals (i.e. a given term cannot be replaced by another that has fewer literals).
A minimum SOP form corresponds to a two-level logic circuit having the fewest gates and the fewest number of gate inputs.
Karnaugh maps and extended karnaugh maps (Feasible for up to 6 variables)
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26. Simplification with XOR
a  0 = a
a  1 = a'
a  a = 0
a  a' = 1
a  b = b  a Commutative Law
(a  b)  c = a  (b  c) = a  b  c Associative Law
a(b  c) = ab  ac Distributive Law
(a  b)' = a  b' = a'  b = ab + a'b' Distributive Law
Ex : :sum = a' . b' . c_in + a' . b . c_in' + a . b' . c_in' + a . b . c_in
sum = (a  b)  c_in = a  b  c_in
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27. Microelectronic Circuit Design
Karnaugh Maps
Karnaugh maps reveal logical adjacencies and opportunities for eliminating a literal from two or more cubes.
K-maps facilitate finding the largest possible cubes that cover all 1s without redundancy.
Requires manual effort.
Example:
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28. Microelectronic Circuit Design
K-map (cont.)
The map shows all possible (16) vertices for a 4-variable function.
Row ordering assures that each row (column) is logically adjacent to its physically adjacent neighboring row (column).
The top-most and bottom-most rows are adjacent.
The left-most and right-most columns are adjacent.
Logically adjacent cells that contain a 1 can be combined.
A rectangular cluster of cells that are logically adjacent can be combined.
Use don't-cares to form prime implicants.
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29. Microelectronic Circuit Design
K-map (cont.)
Corners: a'b'c'd' + a'b'cd' + a'b'c'd' + ab'c'd' = b'd‘
Inner block: a'bc'd + a'bcd + abc'd + abcd = bc'd + bcd = bd
f = b'd' + bd = (b  d)'
Note: Each corner terms imply b'd', and b'd' does not imply another implicant. Therefore, it is a prime implicant. It is also an essential prime implicant. Similarly, bd is an essential prime implicant.
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30. Microelectronic Circuit Design
K-map (cont.)
To form a minimal realization from a Karnaugh map, (1) identify all of the essential prime implicants, using don't-cares as needed (2) use the prime implicants to form a cover of the remaining 1s in the map (ignoring don't-cares).
In general, the covering set of prime implicants is not unique.
Prime Implicants:
m3, m2, m7, m6  a'c (essential)
m2, m10  b'cd' (essential)
m7, m15  bcd
m13, m15  abd
m12, m13  abc' (essential)
Minimal Covers:
(1) a'c, b'cd', bcd, abc'
(2) a'c, b'cd', abd, abc'
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31. General Process to form Minimal Cover
(1) Select an uncovered minterm and identify all of its neighboring cells containing a 1 or an x. A single term (not necessarily a minterm) that covers the minterm and all of its adjacent neighbors having a 1 or an x is an essential prime implicant. Add the term to the set of essential prime implicants.
(2) Repeat (1) until all of the essential prime implicants have been selected.
(3) Find a minimal set of prime implicants that cover the other 1s in the map (do not cover cells containing x).
The above steps may produce more than one possible minimal cover. Select the cover having the fewest literals.
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32. Microelectronic Circuit Design
K-maps and don’t care
Don't cares represent situations where an input cannot occur, or the output does not matter. Use (cover) don't cares when they lead to an improved representation.
Example. Suppose a function is asserted when the BCD representation of a 4-variable input is 0, 3, 6 or 9. f(a, b, c, d) = a'b'c'd' + a'b'cd + abc'd' + abc'd + abcd + abcd' + ab'c'd + ab'cd has 32 literals.
Without don't-cares (16 literals): f(a, b, c, d) = a'b'c'd' + a'b'cd + a'bcd' + ab'c'd
With don't cares (12 literals): f(a, b, c, d) = a'b'c'd' + b'cd + bcd' + ad
f(a, b, c, d) = a'b'c'd' + b'cd + ab + ac'd
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33. Microelectronic Circuit Design
Diode Logic
Diodes can with resistive loads to implement simple logic gates
Diode OR gate
Diode AND gate
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34. Diode Transistor Logic
Since diode gates are limited to AND and OR functions, the diodes can be combined with transistors to complete the basic logic functions such as the following NAND gate
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35. Microelectronic Circuit Design
NMOS Logic Design
MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates
The circuit designer is limited to altering circuit topology and width-to-length, or W/L, ratio since the other factors are dependent upon processing parameters
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36. NMOS Inverter with a Resistive Load
The resistor R is used to “pull” the output high
MS is the switching transistor
The size of R and the W/L ratio of MS are the design factors that need to be chosen
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37. Microelectronic Circuit Design
Silicon Art
In the earlier days of IC design, chip designers were allowed to artistically express themselves on the wafer by creating images with various processing steps
However, today’s modern foundries have stopped this since the graphics did not pass the design rules and were causing fabrication problems
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38. Microelectronic Circuit Design
Silicon Art Examples
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39. Microelectronic Circuit Design
Silicon Art (cont.)
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40. Microelectronic Circuit Design
Silicon Art (cont.)
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41. Microelectronic Circuit Design
Silicon Art (cont.)
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42. Microelectronic Circuit Design
Homework
6.1
6.11
6.16
6.27
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43. Microelectronic Circuit Design
End of Chapter 6
Microelectronic Circuit Design
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