1. S4525A Peripherals & Enhanced FLASH 1 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 1 Peripherals & Enhanced FLASH Enhanced FLASH PIC16F87X and PIC16F62X Enhanced FLASH PIC16F87X and PIC16F62X

2. S4525A Peripherals & Enhanced FLASH 2 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 2 Peripherals & Enhanced FLASH PIC16F87X Features at a Glance l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l Two Capture/Compare/PWMs l USART l 9-bit addressable l High Speed Enhanced SPI  l All 4 SPI modes supported l Microwire  Support Master I 2 C  l Hardware Write to I 2 C devices In-Circuit-Serial Programming  l In-Circuit-Debugger l Parallel Slave Port

3. S4525A Peripherals & Enhanced FLASH 3 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 3 Peripherals & Enhanced FLASH PIC16F62X Features at a Glance l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l Capture/Compare/PWM l USART l 9-bit addressable l High Speed l 2 Comparators In-Circuit-Serial Programming  l Internal RC Oscillator

4. S4525A Peripherals & Enhanced FLASH 4 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 4 Peripherals & Enhanced FLASH Enhanced FLASH Program Memory l The original FLASH concept had bulk erase and an EPROM-like write. l Most MCU-based FLASH devices have bulk/block erase and block writes. l Microchip offers the best of both worlds: l Byte write operation (preceded by erase before write). l Bulk erase operation. l This is Enhanced FLASH. l FLASH Program Memory. l 1,000 erase/write cycles minimum. l Data EEPROM Memory. l 100,000 erase/write cycle minimum. l The original FLASH concept had bulk erase and an EPROM-like write. l Most MCU-based FLASH devices have bulk/block erase and block writes. l Microchip offers the best of both worlds: l Byte write operation (preceded by erase before write). l Bulk erase operation. l This is Enhanced FLASH. l FLASH Program Memory. l 1,000 erase/write cycles minimum. l Data EEPROM Memory. l 100,000 erase/write cycle minimum.

5. S4525A Peripherals & Enhanced FLASH 5 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 5 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Programming/Erase Operation l Program timing controlled by an internal RC oscillator. l Timeout set for ~2mS per word. l When timeout occurs, EEIF flag is set. l Read operation has to be done to verify write. l Write operation sequence has to be followed for each location: l Write 0x55 then 0xAA to EECON2, then set write flag. l Failure to follow sequence aborts write operation. l Advantage: Prevents inadvertent write operations. l Program timing controlled by an internal RC oscillator. l Timeout set for ~2mS per word. l When timeout occurs, EEIF flag is set. l Read operation has to be done to verify write. l Write operation sequence has to be followed for each location: l Write 0x55 then 0xAA to EECON2, then set write flag. l Failure to follow sequence aborts write operation. l Advantage: Prevents inadvertent write operations.

6. S4525A Peripherals & Enhanced FLASH 6 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 6 Peripherals & Enhanced FLASH FLASH Program and Data EEPROM Memory FLASH Program Memory 8K X 14 S. F. R. 256 X 8 Data EEPROM Memory EEADRH EEADR EEDATH EEDATA EECON1 EECON2 13 8 8 14

7. S4525A Peripherals & Enhanced FLASH 7 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 7 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Special Function Registers l EEDATA (10Ch) l Holds data for Data EEPROM. l Holds 8 LSbs of data for Program FLASH. l EEADR (10Dh) l Holds address for Data EEPROM. l Holds 8 LSbs of address for Program FLASH. l EECON1 (18Ch), New Bit EEPGD l EEPROM Read/Write Control Register. l EECON2 (18Dh) l Not a physically implemented register, reads all ‘0’s. l Used exclusively for the memory write sequence. l EEDATA (10Ch) l Holds data for Data EEPROM. l Holds 8 LSbs of data for Program FLASH. l EEADR (10Dh) l Holds address for Data EEPROM. l Holds 8 LSbs of address for Program FLASH. l EECON1 (18Ch), New Bit EEPGD l EEPROM Read/Write Control Register. l EECON2 (18Dh) l Not a physically implemented register, reads all ‘0’s. l Used exclusively for the memory write sequence.

8. S4525A Peripherals & Enhanced FLASH 8 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 8 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Special Function Registers l EEDATH (10Eh) l Used exclusively for Program Memory operations. l Holds the 6 MSbs of the data value. l EEADRH (10Fh) l Used exclusively for Program Memory operations. l Holds the 5 MSbs of the address. l The PIC16F87X devices can calculate program memory checksums. l Checksum calculation allowing program memory integrity. l EEDATH (10Eh) l Used exclusively for Program Memory operations. l Holds the 6 MSbs of the data value. l EEADRH (10Fh) l Used exclusively for Program Memory operations. l Holds the 5 MSbs of the address. l The PIC16F87X devices can calculate program memory checksums. l Checksum calculation allowing program memory integrity.

9. S4525A Peripherals & Enhanced FLASH 9 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 9 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: EECON1 Register EEPGD - - - WRERR WREN WR RD bit7bit0 EEPGD: Program / Data EEPROM Select Bit 1 = Accesses Program Memory 0 = Accesses Data Memory WRERR: EEPROM Error Flag Bit 1 = A write operation is prematurely terminated 0 = The write operation completed WREN: EEPROM Write Enable Bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control Bit 1 = Initiates a write cycle (cleared by hardware only) 0 = Write cycle to the EEPROM is complete RD: Read Control Bit 1 = Initiates a read cycle (cleared by hardware only) 0 = Read cycle from the EEPROM is complete

10. S4525A Peripherals & Enhanced FLASH 10 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 10 Peripherals & Enhanced FLASH FLASH Program Memory: Three Programming Modes  Low Voltage ICSP  mode (Default mode): l Programming at V DD (typically 5V). l RB3/PGM pin dedicated as Program Mode Select. · High Voltage ICSP mode: l High voltage (13V) required on MCLR/V PP pin. l Same ICSP mode as in many other PICmicro ® MCUs. l RB3/PGM pin can be used as normal I/O. ¸ Internal Program Write mode: l Single word writes during program execution. l Example: Calibration constants etc.  Low Voltage ICSP  mode (Default mode): l Programming at V DD (typically 5V). l RB3/PGM pin dedicated as Program Mode Select. · High Voltage ICSP mode: l High voltage (13V) required on MCLR/V PP pin. l Same ICSP mode as in many other PICmicro ® MCUs. l RB3/PGM pin can be used as normal I/O. ¸ Internal Program Write mode: l Single word writes during program execution. l Example: Calibration constants etc.

11. S4525A Peripherals & Enhanced FLASH 11 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 11 Peripherals & Enhanced FLASH FLASH Program Memory: Low Voltage ICSP Mode (Default) RB3 RB6 RB7 V SS V DD CLK DATA V DD PIC16F87X or PIC16F62X Enters LV Programming Mode MCLR PIC16F87X or PIC16F62X V DD

12. S4525A Peripherals & Enhanced FLASH 12 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 12 Peripherals & Enhanced FLASH FLASH Program Memory: Low Voltage ICSP Mode (Default) Sequence: l Low Voltage Programming (LVP) bit in the Configuration Word has to be ‘1’. l RB3/PGM pin is automatically used as a dedicated sense line to enter LV ICSP mode. l V DD and MCLR have to be at same voltage (5V typically). l RB3/PGM pin going from a logic low to high causes LV ICSP. In LV ICSP mode: l RB6 and RB7 are used as serial clock/data lines to serially program the PIC16F87X/PIC16F62X. l All programming operations are enabled. l Exception: LVP bit cannot be re-programmed to ‘0’. Sequence: l Low Voltage Programming (LVP) bit in the Configuration Word has to be ‘1’. l RB3/PGM pin is automatically used as a dedicated sense line to enter LV ICSP mode. l V DD and MCLR have to be at same voltage (5V typically). l RB3/PGM pin going from a logic low to high causes LV ICSP. In LV ICSP mode: l RB6 and RB7 are used as serial clock/data lines to serially program the PIC16F87X/PIC16F62X. l All programming operations are enabled. l Exception: LVP bit cannot be re-programmed to ‘0’.

13. S4525A Peripherals & Enhanced FLASH 13 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 13 Peripherals & Enhanced FLASH FLASH Program Memory: High Voltage ICSP Mode RB6 RB7 PIC16F87X or PIC16F62X V DD CLK DATA PIC16F87X or PIC16F62X enters High Voltage ICSP™ Mode 13V +5V 5V MCLR V DD

14. S4525A Peripherals & Enhanced FLASH 14 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 14 Peripherals & Enhanced FLASH FLASH Program Memory: High Voltage ICSP Mode Sequence: l V DD and MCLR/V PP are at same voltage. l MCLR/V PP is raised to +13V (High Voltage). l PIC16F87X/PIC16F62X enters High Voltage ICSP mode. In High Voltage ICSP Mode: l RB6 and RB7 are used as serial clock/data to serially program the PIC16F87X /PIC16F62X. l All programming operations are enabled. l If LVP bit = 1, RB3/PGM is available as a normal I/O. l High Voltage ICSP mode can be entered, irrespective of the state of the LVP bit. l LVP bit can only be modified in High Voltage ICSP mode. Sequence: l V DD and MCLR/V PP are at same voltage. l MCLR/V PP is raised to +13V (High Voltage). l PIC16F87X/PIC16F62X enters High Voltage ICSP mode. In High Voltage ICSP Mode: l RB6 and RB7 are used as serial clock/data to serially program the PIC16F87X /PIC16F62X. l All programming operations are enabled. l If LVP bit = 1, RB3/PGM is available as a normal I/O. l High Voltage ICSP mode can be entered, irrespective of the state of the LVP bit. l LVP bit can only be modified in High Voltage ICSP mode.

15. S4525A Peripherals & Enhanced FLASH 15 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 15 Peripherals & Enhanced FLASH FLASH Program Memory: Internal Program Write Mode l During normal program execution, a device can write to its own program space. l V DD can be at any operating level: 2.0V to 5.5 V. l Erase automatically precedes the write to the word. l Application Usage: l Storing calibration constants for sensors and transducers in program memory. l Field re-calibration of constants. l Remote re-programming of sections of code excluding code protected areas. l Checksum. l Code revisions. l Tech Briefs: TB025 and TB026. l During normal program execution, a device can write to its own program space. l V DD can be at any operating level: 2.0V to 5.5 V. l Erase automatically precedes the write to the word. l Application Usage: l Storing calibration constants for sensors and transducers in program memory. l Field re-calibration of constants. l Remote re-programming of sections of code excluding code protected areas. l Checksum. l Code revisions. l Tech Briefs: TB025 and TB026.

16. S4525A Peripherals & Enhanced FLASH 16 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 16 Peripherals & Enhanced FLASH FLASH Program Memory: Read/Write Operations Over Voltage l Internal Read/Write Operations: l Can always read any locations at any voltage. l When writes are enabled, can write at any voltage. l External (ICSP) Read/Write Operations: l When enabled: l Read from any location over voltage. l Perform a write to a single location over voltage. l Perform an erase/write cycle to a single location over voltage. l Bulk erase when V DD > 4.5V. l Internal Read/Write Operations: l Can always read any locations at any voltage. l When writes are enabled, can write at any voltage. l External (ICSP) Read/Write Operations: l When enabled: l Read from any location over voltage. l Perform a write to a single location over voltage. l Perform an erase/write cycle to a single location over voltage. l Bulk erase when V DD > 4.5V.

17. S4525A Peripherals & Enhanced FLASH 17 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 17 Peripherals & Enhanced FLASH Data EEPROM Memory: Reading Locations l Program sequence to read Internal Data EEPROM: l Write the desired address to EEADR. l Clear the EEPGD bit, EECON1, which will select Data EEPROM. l Set the RD bit, EECON1. l Data will be available in the EEDATA register in the next instruction cycle. l Program sequence to read Internal Data EEPROM: l Write the desired address to EEADR. l Clear the EEPGD bit, EECON1, which will select Data EEPROM. l Set the RD bit, EECON1. l Data will be available in the EEDATA register in the next instruction cycle.

18. S4525A Peripherals & Enhanced FLASH 18 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 18 Peripherals & Enhanced FLASH Data EEPROM Memory: Reading Locations Program: ;Move to Bank2 ;Write data memory address into the EEADR register ;Move to Bank3 ;Point to Data Memory ;Start the Read Operation, data will be available in the very next Tcy ;Move the data into W Program: ;Move to Bank2 ;Write data memory address into the EEADR register ;Move to Bank3 ;Point to Data Memory ;Start the Read Operation, data will be available in the very next Tcy ;Move the data into W BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRESS MOVWFEEADR BSFSTATUS,RP0 BCFEECON1,EEPGD BSFEECON1,RD BCFSTATUS,RP0 MOVFEEDATA,W

19. S4525A Peripherals & Enhanced FLASH 19 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 19 Peripherals & Enhanced FLASH Data EEPROM Memory: Writing to Locations l Sequence to write data to Internal Data EEPROM: l Write the desired address to EEADR. l Write the desired data to EEDATA. l Clear the EEPGD bit, EECON1 which will select the data memory access. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h followed by AAh to EECON2. l Set the WR bit, EECON1. l Clear the WREN bit, EECON1. l Interrupts can now be enabled. l Wait for WR bit to clear or EEIF to set, which indicates write operation has completed. l Sequence to write data to Internal Data EEPROM: l Write the desired address to EEADR. l Write the desired data to EEDATA. l Clear the EEPGD bit, EECON1 which will select the data memory access. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h followed by AAh to EECON2. l Set the WR bit, EECON1. l Clear the WREN bit, EECON1. l Interrupts can now be enabled. l Wait for WR bit to clear or EEIF to set, which indicates write operation has completed.

20. S4525A Peripherals & Enhanced FLASH 20 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 20 Peripherals & Enhanced FLASH Data EEPROM Memory: Writing to Locations ;Move to Bank2 ;Write desired address to EEADR ;Write desired data to EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Disable interrupts ;Point to data memory ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Enable interrupts ;Disable EEPROM writes, does not affect the current write cycle ;Move to Bank2 ;Write desired address to EEADR ;Write desired data to EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Disable interrupts ;Point to data memory ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Enable interrupts ;Disable EEPROM writes, does not affect the current write cycle BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRESS MOVWFEEADR MOVLWVALUE MOVWFEEDATA BSFSTATUS,RP0 BSFEECON1,WREN BCFEECON1,EEPGD BCFINTCON,GIE MOVLW55h MOVWFEECON2 MOVLWAAh MOVWFEECON2 BSFEECON1,WR BSFINTCON,GIE BCFEECON1,WREN

21. S4525A Peripherals & Enhanced FLASH 21 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 21 Peripherals & Enhanced FLASH FLASH Program Memory: Reading Locations l Write the 8 LSbs of the desired address to EEADR. l Write the 5 MSbs of the desired address to EEADRH. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the RD bit, EECON1. l Next two instruction must be set as NOPs. l Data will be available in the EEDATH:EEDATA registers in the instruction after the NOPs. l Write the 8 LSbs of the desired address to EEADR. l Write the 5 MSbs of the desired address to EEADRH. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the RD bit, EECON1. l Next two instruction must be set as NOPs. l Data will be available in the EEDATH:EEDATA registers in the instruction after the NOPs.

22. S4525A Peripherals & Enhanced FLASH 22 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 22 Peripherals & Enhanced FLASH FLASH Program Memory: Reading Locations ;Move to Bank2 ;Write data memory address into ;the EEADRH:EEADR register ;Point to program memory ;Start the Read Operation, data will ;be available in the third T CY ;Move the data into W ;Move to Bank2 ;Write data memory address into ;the EEADRH:EEADR register ;Point to program memory ;Start the Read Operation, data will ;be available in the third T CY ;Move the data into W BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRH MOVWFEEADRH MOVLWADDRL MOVWFEEADR BSFSTATUS,RP0 BSFEECON1,EEPGD BSFEECON1,RD NOP BCFSTATUS,RP0 MOVFEEDATA,W MOVWFTemp MOVFEEDATH,W

23. S4525A Peripherals & Enhanced FLASH 23 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 23 Peripherals & Enhanced FLASH FLASH Program Memory: Writing to Locations l Write the desired address to EEADRH:EEADRL. l Write the desired data to EEDATH:EEDATA. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h to EECON2 followed by AAh to EECON2. l Set the WR bit, EECON1. l Next two instructions must be NOPs. l CPU now halts while memory is programmed (~2mS), this is NOT sleep mode as the clocks and peripherals continue to run. l When the write is completed, program execution starts at the instruction just after the two NOPs (above). l Clear the WREN bit, EECON1. l Write the desired address to EEADRH:EEADRL. l Write the desired data to EEDATH:EEDATA. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h to EECON2 followed by AAh to EECON2. l Set the WR bit, EECON1. l Next two instructions must be NOPs. l CPU now halts while memory is programmed (~2mS), this is NOT sleep mode as the clocks and peripherals continue to run. l When the write is completed, program execution starts at the instruction just after the two NOPs (above). l Clear the WREN bit, EECON1.

24. S4525A Peripherals & Enhanced FLASH 24 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 24 Peripherals & Enhanced FLASH FLASH Program Memory: Writing to Locations ;Move to Bank2 ;Write desired address to EEADRH:EEADR ;Write desired data to EEDATH:EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Point to program memory ;Disable interrupts ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Instruction is executed normally ;Instruction is ignored, processor halts ;Enable interrupts ;Disable EEPROM writes ;Move to Bank2 ;Write desired address to EEADRH:EEADR ;Write desired data to EEDATH:EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Point to program memory ;Disable interrupts ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Instruction is executed normally ;Instruction is ignored, processor halts ;Enable interrupts ;Disable EEPROM writes BANKSELEEADDRH MOVLWADDRH MOVWFEEADRH MOVLWADDRL MOVWFEEADR MOVLWDATAH MOVWFEEDATH MOVLWDATAL MOVWFEEDATA BSFSTATUS,RP0 BSFEECON1,WREN BSFEECON1,EEPGD BCFINTCON,GIE MOVLW55h MOVWFEECON2 MOVLWAAh MOVWFEECON2 BSFEECON1,WR NOP BSFINTCON,GIE BCFEECON1,WREN

25. S4525A Peripherals & Enhanced FLASH 25 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 25 Peripherals & Enhanced FLASH Feature Comparison DevicePIC16C74APIC16C74BPIC16F874PIC16C77PIC16F877 Operating Freq.DC-20MHz Resets/DelaysPOR,BOR PWRT,OST Prog. Mem4K EPROM 4K FLASH8K EPROM8K FLASH Data Mem192 368 EEPROM001280256 Interrupts12 141214 I/O Ports33 Timers33333 CCP22222 SPIYYY, Enh. I2CSlave Mstr/SlaveSlaveMstr/Slave USARTYYY, 9-bitY Parallel PortYYYYY 8-bit A/D8 ch. 10-bit A/D8 ch. ICSP/ICDY/N Y/YY/NY/Y

26. S4525A Peripherals & Enhanced FLASH 26 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 26 Peripherals & Enhanced FLASH Bank0 Bank1 Bank2 Bank3 Special Function Registers PIC16C77 PIC16F877 00h 180h 1Fh 19Fh 00h 1Fh 180h 19Fh