1. Chapter 4: MEMORY
Internal Memory

2. Introduction
Memory refers to the physical devices used to store sequences of instructions (programs) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic devices.
Primary memory is used for the information in physical systems which are fast (i.e. RAM), as a distinction from secondary memory, which are physical devices for program and data storage that are slow to access but offer higher memory capacity.
Primary memory stored on secondary memory is called ”virtual memory“ . It is a system where all physical memory is controlled by the operating system. When a program needs memory, it requests it from the operating system.

3. Semiconductor Memory Types
Category
Erasure
Write Mechanism
Volatility
RAM
Read-write memory
Electrically, byte-level
Electrically
Volatile
ROM
Read-only memory
Not possible
Masks
Nonvolatile
PROM
EPROM
Read-mostly memory
UV light, chip-level
EEPROM
Flash memory
Electrically, block-level

4. Volatile v. Non-volatile
There are two main types of semiconductor memory: 
Non-volatile
computer memory that can retain the stored information even when not powered
Example: flash memory (sometimes used as secondary, sometimes primary computer memory) and xROMs memory (used for firmware such as boot programs).
Volatile
computer memory that requires power to maintain the stored information
Example: DRAM and fast CPU cache memory (typically SRAM, which is fast but energy-consuming and offer lower memory capacity per area unit than DRAM)

5. Semiconductor memory
Organized into memory cells or bistable flip-flops, each storing one binary bit (0 or 1).
Memory cells are grouped into words of fix word length, such as 1, 2, 4, 8, 16, 32, 64 or 128 bit.
Each word can be accessed by a binary address of N bit, making it possible to store 2 raised by N words in the memory.
Processor registers normally are not considered as memory, since they only store one word and do not include an addressing mechanism

6. Semiconductor Memory RAM
Misnamed as all semiconductor memory is random access
Read/Write
Volatile
Temporary storage
Static or dynamic

7. Memory Cell Operation
Has 3 functional terminals capable carrying electrical signal
Select: memory cell for a read or write operation
Control: indicates read or write
Data in/sense

8. Bits stored as charge in capacitors Charges leak
Dynamic RAM
Bits stored as charge in capacitors
Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
Level of charge determines value
Dynamic refers to this tendency of the stored charge to leak away, even with power continuously applied

9. Dynamic RAM Structure & Operation
Address line active when bit read or written
Transistor switch closed (current flows)
Write
Voltage to bit line
High for 1 Low for 0
Then signal address line
Transfers charge to capacitor
Read
Address line selected
transistor turns on
Charge from capacitor fed via bit line to sense amplifier
Compares with reference value to determine 0 or 1
Capacitor charge must be restored

10. Bits stored as on/off switches No charges to leak
Static RAM
Bits stored as on/off switches
No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
Uses flip-flops

11. Stating RAM Structure & Operation
Transistor arrangement gives stable logic state
State 1
C1 high, C2 low
T1 T4 off, T2 T3 on
State 0
C2 high, C1 low
T2 T3 off, T1 T4 on
Address line transistors T5 T6 is switch
Write – apply value to B & compliment to B
Read – value is on line B

12. SRAM v DRAM Both volatile Dynamic cell Static
Power needed to preserve data
Dynamic cell
Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
Static
Faster
Cache

13. Microprogramming (see later) Library subroutines
Read Only Memory (ROM)
Permanent storage
Nonvolatile
Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables

14. Written during manufacture Programmable (once)
Types of ROM
Written during manufacture
Very expensive for small runs
Programmable (once)
PROM
Needs special equipment to program
Read “mostly”
Erasable Programmable (EPROM)
Erased by UV
Electrically Erasable (EEPROM)
Takes much longer to write than read
Flash memory
Erase whole memory electrically

15. Organisation in detail
A 16Mbit chip can be organised as 1M of 16 bit words
A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on
A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4 capacity

16. Refreshing
Refresh circuit included on chip
Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance

17. Typical 16 Mb DRAM (4M x 4) All DRAMs require refresh operation.
Simple technique: refresh counter steps thru all the rows values. For each row, output line from refresh counter are supplied to the row decoder and RAS line is activated. Then data are read out and written back into the same location.

18. Packaging Data pin for RAM are I/O. Why?
DRAM: 11 address pins are needed for 4M because address is mux’d

19. 256kByte Module Organisation
RAM chip contains only 1 bit per word.
For 256K 8-bit words, 18-bit address is needed. Address is presented to 8 256k X 1-bit chips, each of which provides the I/O of 1 bit.
For larger memory, an array of chip is needed

20. 1MByte Module Organisation
1M word, 20 address lines are needed.
18 LSB are routed to all 32 modules
High order 2 bits are input to a group select logic module that sends EN signal to one of the 4 columns of modules

21. Interleaved Memory
Collection of DRAM chips
Grouped into memory bank
Banks independently service read or write requests
K banks can service k requests simultaneously

22. Detected using Hamming error correcting code
Error Correction
Semiconductor memory system is subject to errors: hard failures and soft errors
Hard Failure
Permanent defect
Soft Error
Random, non-destructive
No permanent damage to memory
Detected using Hamming error correcting code

23. Error Correcting Code Function
No errors are detected. The fetched data bits are sent out
If error then correct the error. If ok then produced a corrected set of M Bits to be sent out
If error no correction then condition is reported

24. Advanced DRAM Organization
Basic DRAM same since first RAM chips
Enhanced DRAM
Contains small SRAM as well
SRAM holds last line read (c.f. Cache!)
Cache DRAM
Larger SRAM component
Use as cache or serial buffer

25. Synchronous DRAM (SDRAM)
Access is synchronized with an external clock
Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and fire it out in block
DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

26. SDRAM
Perform best when it is transferring large blocks of data serially

27. SDRAM Read Timing

28. Adopted by Intel for Pentium & Itanium Main competitor to SDRAM
RAMBUS
Adopted by Intel for Pentium & Itanium
Main competitor to SDRAM
Vertical package – all pins on one side
Data exchange over 28 wires < cm long
Bus addresses up to 320 RDRAM chips at 1.6Gbps
Asynchronous block protocol
480ns access time
Then 1.6 Gbps

29. RAMBUS Diagram

30. SDRAM can only send data once per clock
DDR SDRAM
SDRAM can only send data once per clock
Double-data-rate SDRAM can send data twice per clock cycle
Rising edge and falling edge

31. DDR SDRAM Read Timing

32. Simplified DRAM Read Timing

33. Integrates small SRAM cache (16 kb) onto generic DRAM chip
Cache DRAM
Mitsubishi
Integrates small SRAM cache (16 kb) onto generic DRAM chip
Used as true cache
64-bit lines
Effective for ordinary random access
To support serial access of block of data
E.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAM buffer
Subsequent accesses solely to SRAM

34. END OF INTERNAL MEMORY