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Published byRussell Powers Modified over 9 years ago
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What is µP? “An integrated circuit containing … a central processing unit (CPU) and a means to access external memory” -- (Ball 2000)
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Memory Memory types –RAM –ROM, PROM –EPROM, EEPROM, Flash RAM Memory Cell inactive read write 0x 1 0 xx 1 1 yx y
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Bus Collection of signal lines -- uni(bi)directional Operation represented using timing diagrams Clocked vs Asynchronous separate data and address buses
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System Bus Control Signals Multiple users? –arbitration –sender/reciever id Multiplexed? –data ready –clock Block Transfer –busy PCI Bus -- Read
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CPU Architecture VonNeumann –code can be modified (accidentally) CPU Data Code Data Code Data Code Harvard –data access does not slow code access –instruction and data widths unrelated
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CPU Internals Registers: Storage for data Control Unit: issues control path signals (micro-operations) to other parts of CPU ALU: manipulates data in response to signals from the control unit Bus: Transports data between ALU and registers
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CPU Architecture Accumulator Stack Register w=1; w=w+2; Ra=1; Rb=2; Ra=Ra+Rb; 23 11 00 01130 212131 Push 1 Push 2 Add
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Instruction vs. Micro-operation Write
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Add Instruction - Fetch AddressPnemonic Value 1100load 100 0001 1101 add 510 0101 1110jmp 1100 ………. CU PC IR 1 2 3 1101 1110 00 0001 10 0101 110110 0101 1 3 0001
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Add Instruction - Indirect (Decode) CU IR 1ALU operation 0 add 0bit 3 1bit 2 0bit 1 1bit 0 0101 Control signals
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Add Instruction - Execute CU 1 2 3 0101 13 0001 ALU 11 0110 Status flags add
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RISC vs. CISC Single-cycle instruction execution –Simple, fixed instruction format –few instructions and addressing modes –Hardwired micro-operations Memory Access –Load/Store design –High-performance memory (registers/cache). Predictable Speed/Performance Multi-cycle instruction execution –Variable size instruction format –Micro-programmed instruction set Smaller program size (# of instructions) Memory Access –Multiple addressing modes Optimization Complexity
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Pipelining Fetch1Indirect1Execute1Write1Fetch2Indirect2Execute2Write2Fetch1Indirect1Execute1Write1 Fetch4Indirect4Execute4Write4 Fetch2Indirect2Execute2Write2 Fetch3Indirect3Execute3Write3 Fetch5Indirect5Execute5Write5 Assumptions: – stages all have same duration –no branching –consecutive instructions are independent
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Architecture vs. Organisation –Bit Widths –Instruction set CPU components –bus operations –parallel/replicated functions? –Pipelining –RISC/CISC –Control signals –Micro-operation set external interface –access times –RAM: static vs. dynamic physical layout –manufacturing process –logic family –track length –power/heat considerations
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Moveregisterregister Store register memory Load memoryregister Exchangeregisterregister Swap lo-nibblehi-nibble Clear00000000register Set 11111111register Push registerstack Popstackregister Machine Instructions Data transfer
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Machine Instructions Arithmetic/Logical increment, decrement, not absolute, negate, two’s-complement add, subtract, multiply, divide and, or, exclusive-or register OP register
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Machine Instructions:Bit--Logical ··· x == x? x y ? == Bit-set, Bit-clear Bit-test Bit-compare Shift Rotate
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Machine Instructions Control transfer/Special purpose Program flow –skip[PC]=[PC]+1 –branch[PC]=? –call push [PC]; [PC]=? –returnpop [PC] Processing pause –nop1 cycle delay –sleepwait for event –wait? cycle delay Special: –input/output –data conversion –system operation Compound –conditional branch IF BIT-TST BRANCH –return with value LOAD VALUE RETURN
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Machine Instruction Examples Add Load Branch Arithmetic Data Transfer Control Transfer Address Mnemonic Value 1100load 100 0001 1101 add 510 0101 1110jmp 1201 1110 Operand 4 bits Op-code 2 bits
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Addressing Modes Displacement Variants Relative Base Register Indexing Post-Indexing Pre-Indexing
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How Many Operands? 0-operand PUSH 5 PUSH 6 ADD 1-operand LOAD 5 ADD 6 2-operand LOAD R1,5 ADD R1, 6 3-operand LOAD R2, 5 ADD R1, R1, R2 StackAccumulator Register
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Variable length instructions, Operand Specified Addressing Modes
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System Reset / Program Launch Branch 0100 0000 Load 5 Add 2 …... 0100 0101 0110 End 1110 Operating System Start Halt
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Development Software Tool Chain IDE Download Program Compiler Linker Simulator In-circuit Debugger Editor Live
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