1. Design of Advanced Erase Mechanism for NOR Flash EEPROM Amit Berman, June 2006 Intel Corporation

2. Agenda  Flash Memory Introduction  Project’s Targets  Current Erase Solution  Proposed Methodology for New Mechanism  Lab Results and Evaluation  Conclusions  Questions Session AEM project

3. Flash Memory Introduction AEM project Substrate p- Drain n+ Source n+ Tox FG ONO Gate Bit-line (Vd) Control Gate Wordline (Vg) - - - - - - Source (Vs) - -  What is Flash? - Non-Volatile Memory - Examples: Cell-phone OS, PC BIOS  MOSFET with floating gate: Information is stored as electrons in the floating gate - Many Electrons – Logic ‘0’ - Few Electrons – Logic ‘1’  Best memory alternative: Low cost, Low power, High density and High speed.

4. Flash Memory Introduction (2) AEM project Id (  A) Vg (V) E 5 0 12 3 45 R P Program - CHEErase – FN tunnelingRead – Sensing Substrate p-p- Drain n+ Source n+ Tox FG ONO Gate Bit-line (Float) Control Gate Wordline Vg << 0 - - -- - - - Source (Float) - - - - - - -- - Vwell=positive Vg Substrate p- Drain n+ Source n+ Tox FG ONO Gate Vread Control Gate Vcc - - - - - - Source - - Sense Amp Output REF SEN Drain I I

5. Project ’ s Targets AEM project  Speed-up Erase operation (bottleneck 0.9sec per block)  Improve product reliability by reducing “Post Erase Repair” phenomena (DPM)  Reduce product test time

6. Current Erase Solution  Channel Erase Pulses  Block basis (shared bulk)  Increasing pulse series  Erase Verify – Vt Measurement (read) until all block is erased  Disadvantages:  Since not all cells are similar,some will be over-erased : always logic ‘1’.  Post erase repair – soft programming is needed. AEM project

7. Proposed Methodology  Detect an “Optimum Point” on channel erase where fast and normal bits are erased but slow-erased bits are programmed.  Handle Slow-erased bits with “special care” – erase via drain.  Reduce over-erased cells to minimum. AEM project

8. Lab Results and Evaluation  We can identify slow-erased bit by constant charge loss in each erase pulse. Flash Vt will be briefly reduced.  Model for slow-erased bits: on erase pulse #10.  Trade-off between reducing over-erased bits and erase speed.  Erase operation speed is improved from 0.9sec per block to 0.7sec per block. PP project

9. Conclusions  Potential speedup: future implementation on embedded flash microcode and on test program platforms.  Quality and Reliability check is needed.  Examine cost-effective trade-off with Q&R and device operation speed. PP project

10. Questions Session AEM project