1. Memory Cell Operation

2. Semiconductor Memory RAM
Misnamed as all semiconductor memory is random access
Read/Write
Volatile
Temporary storage
Static or dynamic

3. Dynamic RAM Bits stored as charge in capacitors (analogue)
Need refresh circuits even when powered
Simpler construction
Smaller per bit (More dense)
Less expensive
Slower
Main memory

4. Dynamic RAM Structure

5. Static RAM Bits stored as on/off switches (Digital)
Does not need refresh circuits
More complex construction
Larger per bit (Less dense)
More expensive
Faster
Cache memory

6. Static RAM Structure

7. Read Only Memory (ROM) Permanent storage Nonvolatile used in:
Microprogramming
Library subroutines
Systems programs (BIOS)
Function tables

8. Types of ROM ROM: Written during manufacture
Very expensive for small runs
There is no room for error
PROM: Programmable (once) ROM
needs special equipment to program
Read “mostly”
Erasable Programmable (EPROM)
Erased by UV (more expensive than PROM)
Electrically Erasable (EEPROM)
Takes much longer to write than read
More expensive and less dense than EEPROM
Flash memory
Intermediate between EPROM and EEPROM in both cost and functionality

9. Semiconductor Memory Types

10. Advanced DRAM Organization
Synchronous DRAM
Double-data-rate Synchronous DRAM
Rambus DRAM
Cache DRAM (Integrates small SRAM onto generic DRAM chip)

11. Synchronous DRAM (SDRAM)
Access is synchronized with an external clock
Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and fire it out in block

12. DDR SDRAM SDRAM can only send data once per clock cycle
Double-data-rate SDRAM can send data twice per clock cycle
Theoretically
DDR module transfer data at a clock rate in the range of 200 to 600 MHz
DDR2 module transfers at a clock rate of 400 to 1066 MHz
DDR3 module transfers at a clock rate of 800 to 1600 MHz

13. Interleaved Memory Collection of DRAM chips grouped into memory bank
Banks independently service read or write requests
K banks can service k requests simultaneously
To speed up, consecutive words of memory are stored in different banks

14. Memory decoding

15. Two-dimensional decoding

16. Address multiplexing

17. Module Organization A 16Mbit chip can be organized as 1M X16 bit words
A bit per chip system has 16 of 1Mbit chips with 1bit of each word (1MX1bit)
A 16Mbit chip can be organized as a 2048 x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address

18. 256kByte Module Organization

19. 1MByte Module Organisation

20. Error Correction Hard Failure Soft Error
Permanent defect
Soft Error
Random, non-destructive
No permanent damage to memory
Detected using error-correcting code (such as Hamming code)

21. Error Correcting Code Function

22. Hamming Error-Correcting Code

23. Number of check bits 2K - 1 ≥ M + K
the comparison logic receives as input two K-bit values
A bit-by-bit comparison is done by taking the exclusive-OR of the two inputs
The result is called the syndrome word
2K - 1 ≥ M + K
Where M is the number of data bits (how many check bits are required for a byte?)

24. Hamming code

25. Hamming code characteristics
If the syndrome contains all 0s, no error has been detected
If the syndrome contains one and only one bit set to 1, then an error has occurred in one of the 4 check bits. No correction is needed
If the syndrome contains more than one bit set to 1, then the numerical value of the syndrome indicates the position of the data bit in error. This data bit is inverted for correction

26. Example Correct data 00111001 C1= , C2= , C4= , C8= Stored as
Retrieved data
Syndrome word=

27. RQ: 5.3, 5.4, 5.5, 5.6, 5.7, 5.9, 5.10, 5.11
P: 5.2, 5.3, 5.4, 5.10, 5.11, 5.12, 5.13