1. D. Golimowski2010 STScI Calibration Workshop1 ACS after SM4: New Life for an Old Workhorse David Golimowski Space Telescope Science Institute 22 July 2010

2. D. Golimowski2010 STScI Calibration Workshop2 ACS Chronology March 2002: ACS installed in HST during Servicing Mission 3B (STS-109) June 2006: Failure of Side 1 LVPS. Switch to redundant Side 2 electronics. All camera operations restored. January 2007: Failure of Side 2 LVPS or APB. Loss of WFC and HRC operations; SBC still operational. May 2009: ACS-R hardware installed during Servicing Mission 4 (STS-125). WFC and SBC pass Aliveness and Functional Tests; HRC not recovered. STS-125 astronauts Drew Feustel and John Grunsfeld during EVA-3

3. D. Golimowski2010 STScI Calibration Workshop3 The ACS Repair (ACS-R) Four major components of ACS-R: CCD Electronics Box Replacement (CEB-R) Low Voltage Power Supply Replacement (LVPS-R) Power Intercept Element (PIE) Power Output Element (POE)

4. D. Golimowski2010 STScI Calibration Workshop4 The CEB-R Main CEB-R features: Teledyne SIDECAR* ASIC** permits optimization of WFC performance via adjustment of CCD clocks, biases, and pixel transmission timing Built in oscilloscope mode (O-mode) that allows sensing of analog signal from each output amplifier * System for Image Digitization, Enhancement, Control, and Retrieval ** Application Specific Integrated Circuit

5. D. Golimowski2010 STScI Calibration Workshop5 WFC Optimization Campaign (1) Ground testing: Verified performance of CEB-R with flight-spare WFC, but not actual flight WFC  SITe CCD performance highly variable Revealed non-ideal transient settling behavior in external preamp  Preamp not replaced by ACS-R, so behavior with CEB-R not verifiable Revealed noise dependence on timing of data transmission from CEB-R to MEB On-orbit testing: To satisfy requirement that WFC perform at least as well as before, CEB-R must accommodate above uncertainties via flexible, programmable settings Need iterative campaign to optimize CCD read noise, gains, linearity, full well depth, CTE, cross-talk

6. D. Golimowski2010 STScI Calibration Workshop6 WFC Optimization Campaign (2) Strategy: Perform up to 8 iterations of comprehensive CCD performance tests and exploratory adjustments of bias voltages, clock rails, and data transmission timing via uplinked commands to ASIC Start with pre-failure default CCD voltages and timing patterns as baseline, then vary appropriate values to investigate specific conditions Converge to optimal settings; truncate Optimization Campaign if possible Select default CDS mode (dual-slope integrator or clamp-and-sample) Modify flight software and assembly code to conform to optimal settings

7. D. Golimowski2010 STScI Calibration Workshop7 OC Results OC began 28 May 2009 with pre-SM4 default (old CEB) voltage & timing settings Initial performance matched or exceeded projections and expectations. Dark current, CTE, and hot pixels consistent with prolonged radiation exposure. Dual-slope integrator (DSI) selected as default CDS mode Gradient of 5-10 DN caused by slow drift of bias reference voltage after readout of each row of pixels. Gradient is stable and removable. Low level (±1 DN) bias stripes caused by 1/f noise generated by ASIC during bias voltage offset. OC ended 3 Jun 2009 due to anomaly in WFC2 for non-default V OD. Pre-SM4 default settings adopted for all post-SM4 operations.

8. D. Golimowski2010 STScI Calibration Workshop8 WFC Performance Summary Characteristic Jan 2007 (measured) May 2009* (projected) Problematic* Post SM4 (measured) Read noise (e – ; gain = 2) C&S: 5.5DSI: 4.010 DSI: 3.9-4.7 C&S: 4.4-5.7 Dark current (e – /pix/hr)10.71510020-25 Hot pixels (%)0.681.11.51.1 Full well depth (e – )84,000 40,000> 80,000 Non-linearity (%) < 0.1 0.5< 0.2 CTE (EPER; 1620 e – )0.9999490.9999210.99990.99989 Cross-talk (50 ke – hot pixels) 4x10 -5 4x10 -4 (5±4)x10 -5 Bias shift** (%)0.02< 0.1< 0.2 0.02-0.30 (before correction) * Projected and problematic values from Gilliland et al. 2008 (TIR ACS 2008-04). **Signal-dependent shift due to incomplete settling of reference voltage in DSI high-pass filter. Effect can be corrected by software algorithm.      

9. D. Golimowski2010 STScI Calibration Workshop9 WFC Dark Current History 12 hr anneal6 hr anneal -77 C-81 C 6 hr anneal -77 C

10. D. Golimowski2010 STScI Calibration Workshop10 WFC CTE History EPER test shows worse than expected CTE degradation (0.99989 vs. 0.99992), but… Evolution of deferred-charge trails from hot pixels show degradation consistent with expectation Pre-SM4 correction formulae for WFC and HRC aperture photometry valid for post-SM4 data (Chiaberge ISR 2009-01) Empirical pixel-based CTE corrections now a reality ! (Next talk by Jay Anderson)

11. D. Golimowski2010 STScI Calibration Workshop11 WFC Bias and Dark Frames Superbias - 1 full anneal cycle (DSI; 34 frames) Superdark - 1/2 anneal cycle (DSI; 24 frames) bias “gradient” (5-10 DN) bias stripes (± 1 DN)

12. D. Golimowski2010 STScI Calibration Workshop12 Bias Stripe Effect Caused by 1/f noise (1 mHz to 1 Hz) in bias reference voltage after CDS (Talks by Bernie Rauscher and Markus Loose) Appears in both DSI and C&S frames Stripes vary by  ~ 0.75 e – ; negligible relative to read noise Noise is correlated; may affect photometry of the faintest sources Software developed to mitigate effect (Poster A2 by Norman Grogin)

13. D. Golimowski2010 STScI Calibration Workshop13 Bias Stripe Removal (before)(after)

14. D. Golimowski2010 STScI Calibration Workshop14 Cross Talk NGC 4701 (pre-SM4)NGC 6217 (post-SM4) (See poster A3 and ISR ACS 2010-02 by Anatoly Suchkov, et al.) Gain = 2 e – /DN

15. D. Golimowski2010 STScI Calibration Workshop15 Summary ACS record after SM4: 1 win (WFC), 1 loss (HRC), 1 tie (SBC) ACS-R Optimization Campaign showed that WFC read noise, linearity, full-well depth, and cross-talk match or exceed pre-SM4 levels CTE, hot pixels, dark current have degraded to levels consistent with prolonged exposure to HST ’ s radiation environment Bias gradient of 5-10 DN caused by a slow drift of the DSI reference voltage during and after the readout of each row of pixels; stable and removable Low level (  1 DN) bias stripes caused by 1/f noise in bias reference voltage set after CDS stage of signal processing chain; not reproducible from frame to frame Algorithms for mitigating bias stripes and pixel-to-pixel CTE correction will be available to users very soon; STScI is investigating implementation into calacs.

16. D. Golimowski2010 STScI Calibration Workshop16 ACS-R Design and Optimization Teams PI: Ed Cheng (Conceptual Analytics) STScI: George Chapman, Marco Chiaberge, Tyler Desjardins, Tracy Ellis, David Golimowski, Norman Grogin, Pey-Lian Lim, Ray Lucas, Aparna Maybhate, Max Mutchler, Merle Reinhart, Marco Sirianni (ESA/ESTEC), Linda Smith, Anatoly Suchkov, Alan Welty, Tom Wheeler GSFC: Steve Arslanian, Kevin Boyce, Darryl Dye, Olivia Lupie, Kathleen Mil, Barbara Scott, Beverly Serrano, Augustyn Waczynski, Erin Wilson Teledyne: Markus Loose (Markury Scientific), Raphael Ricardo