1. ECE 545 Digital System Design with VHDL
Course web page:
ECE web page  Courses  Course web pages
 ECE 545

2. Research and teaching interests:
Kris Gaj
Research and teaching interests:
reconfigurable computing
computer arithmetic
cryptography
network security
Contact:
The Engineering Building, room 3225
Office hours: Monday, Tuesday, Wednesday :00-7:00 PM

3. MS in Computer Engineering
ECE 545
Part of:
MS in Computer Engineering
Required course in two concentration areas:
Digital Systems Design
Microprocessor and Embedded Systems
Elective course in the remaining concentration areas
MS in Electrical Engineering
Elective

4. Courses Design level Digital System Design with VHDL Computer
Arithmetic
VLSI Design
for ASICs
VLSI Test
Concepts
algorithmic
ECE
645
ECE
545
register-transfer
ECE
681
ECE
682
gate
ECE
586
transistor
Digital
Integrated
Circuits
ECE
680
layout
Physical VLSI Design
Semiconductor
Device Fundamentals
MOS Device
Electronics
ECE 584
ECE684
devices

5. DIGITAL SYSTEMS DESIGN
Concentration advisors: Kris Gaj, Ken Hintz
ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL,
Aldec/Synplicity/Xilinx
2. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL or Verilog,
3. ECE 681 VLSI Design for ASICs – N. Klimavicz, project/lab, back-end ASIC design with Synopsys tools
4. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri
5. ECE 682 VLSI Test Concepts
– T. Storey

6. Grading Scheme Project - 40% Midterm Exam - 20% Final Exam - 30%
Homework %
Project %
Midterm Exam %
Final Exam %

7. Midterm exam 1 2 hours 30 minutes in class design-oriented
open-books, open-notes
practice exams will be available on the web
Tentative date:
Thursday, October 21st

8. Final exam 2 hours 45 minutes in class design-oriented
open-books, open-notes
practice exams will be available on the web
Date:
Wednesday, December 16, 7:30-10:15pm

9. infeasible to find such
Hash Function
arbitrary length m
message
hash
function h
It is computationally
infeasible to find such
m and m’ that
h(m)=h(m’)
h(m)
hash value
fixed length

10. Main Application: Digital Signature
HANDWRITTEN
DIGITAL
A6E3891F2939E38C745B
CA345BEF5349
245CBA653448E349EA47
Main Goals:
unique identification
proof of agreement to the contents
of the document

11. Typical Digital Signature Scheme
Alice
Bob
Message
Signature
Message
Signature
Hash
function
Hash
function
Hash value 1
Hash value
yes no
Hash value 2
Public key
cipher
Public key
cipher
Alice’s private key
Alice’s public key

12. Handwritten and Digital Signatures
Common Features
Handwritten signature
Digital signature
1. Unique
2. Impossible to be forged
3. Impossible to be denied by the author
4. Easy to verify by an independent judge
5. Easy to generate

13. Handwritten and Digital Signatures
Differences
Handwritten signature
Digital signature
6. Associated physically
with the document
7. Almost identical
for all documents
8. Usually at the last
page
6. Can be stored and
transmitted
independently
of the document
7. Function of the
document
8. Covers the entire

14. Cryptographic Standards
So how the cryptographic standards
have been created so far?

15. NSA National Security Agency (also known as “No Such Agency”
or “Never Say Anything”)
Created in 1952 by president Truman
Goals:
designing strong ciphers (to protect U.S. communications)
breaking ciphers (to listen to non-U.S. communications)
Budget and number of employees kept secret
Largest employer of mathematicians in the world
Larger purchaser of computer hardware

16. NSA-developed Cryptographic Standards
Block Ciphers
1977
1999
2005
DES – Data Encryption Standard
Triple DES
1993
1995
2003
Hash Functions
SHA-1–Secure Hash Algorithm
SHA-0
SHA-2
1970
1980
1990
2000
2010
time

17. Cryptographic Standard Contests
IX.1997
X.2000
AES
15 block ciphers  1 winner
NESSIE
I.2000
XII.2002
CRYPTREC
XI.2004
V.2008
34 stream ciphers  4 SW+4 HW winners
eSTREAM
X.2007
XII.2012
51 hash functions  1 winner
SHA-3
time

18. Criteria used to evaluate cryptographic
transformations
Security
Hardware
Efficiency
Software
Efficiency
Flexibility

19. Software or hardware? SOFTWARE HARDWARE security of data
during transmission
speed
random key
generation
access control
to keys
low cost
resistance to
side-channel attacks
flexibility
(new cryptoalgorithms,
protection against new attacks)
tamper resistance

20. Primary efficiency indicators
Hardware
Software
Speed
Memory
Memory
Speed
Area
Power
consumption

21. Efficiency parameters
Latency
Throughput = Speed
Mi+2 Mi
Mi+1 Mi
Time to
encrypt/decrypt
a single block
of data
Encryption/
decryption
Encryption/
decryption
Number of bits
encrypted/decrypted
in a unit of time
Ci+2 Ci
Ci+1 Ci
Block_size · Number_of_blocks_processed_simultaneously
Throughput =
Latency

22. Advanced Encryption Standard (AES) Contest
June 1998
15 Candidates
from USA, Canada, Belgium,
France, Germany, Norway, UK, Israel,
Korea, Japan, Australia, Costa Rica
Round 1
Security
Software efficiency
Flexibility
August 1999
Round 2
5 final candidates
Security
Mars, RC6, Rijndael, Serpent, Twofish
Hardware efficiency
October 2000
1 winner: Rijndael
Belgium

23. Speed of the final AES candidates in Xilinx FPGAs
Speed [Mbit/s]
K.Gaj, P. Chodowiec, AES3, April, 2000
500
450
400
350
300
250
200
150
100 50
Serpent
Rijndael
Twofish
RC6
Mars

24. Survey filled by 167 participants of
the Third AES Conference, April 2000
# votes
100 90 80 70 60 50 40 30 20 10
Rijndael
Serpent
Twofish
RC6
Mars

25. Results of the NSA group
ASICs
Speed [Mbit/s]
AES3, April, 2000
700
NSA
ASIC
GMU
FPGA
606
600
500
414
431
400
300
202
177
200
143
105
103 61
100 57
Rijndael
Serpent
Twofish
RC6
Mars

26. Efficiency in software: NIST-specified platform
200 MHz Pentium Pro, Borland C++
Speed [Mbits/s]
128-bit key
192-bit key
256-bit key 30 25 20 15 10 5
Rijndael
RC6
Twofish
Mars
Serpent

27. NIST Report: Security Security MARS High Serpent Twofish Rijndael
AES Final Report, October 2000
Security
MARS
High
Serpent
Twofish
Rijndael
Adequate
RC6
Simple
Complex
Complexity

28. eSTREAM Stream Cipher Comparison
Part of the GMU Fall 2006 & Fall 2007 graduate courses
ECE 545 Introduction to VHDL
Individual 6-week project
4 students working independently on each eSTREAM cipher
best code for each algorithm selected at the end
of the semester
selected designs verified and revised in order to assure
correct functionality
standard interface & control
possibly uniform design & coding style

29. Comparison of 4 Focus Hardware-Oriented Stream Ciphers
FPGA: Xilinx Spartan 3 family
Throughput
[Mbit/s]
Best
T64
12000
10000
Trivium
8000
T32
6000
4000
T16
G16
Phelix
2000
Grain
AES G1
Mickey-128
Worst
Area
[CLB slices]
200
400
600
800
1000
1200
1400

30. Comparison of 8 Final Candidates Sorted by Minimum Area and Maximum Throughput/Area
(slices)
Throughput/Area
(Mbps/slices)
Grain v1 44
Trivium (x64)
39.26
Grain 128 50
Grain 128 (x32)
7.97
Trivium
Grain v1 (x16)
5.98
DECIM v2 80
4.80
DECIM 128 89
F-FCSR-16
4.53
MICKEY 2.0
115
4.45
MICKEY
176
3.92
Moustique
278
F-FCSR-H v2
3.23
342
2.03
344
1.27
Grain v1 (x16)
348
0.81
473
0.58
534
0.49
Pomaranch
648
Edon80
0.10
1284
0.08

31. Conclusions from the Comparison of the eSTREAM Candidates in Hardware
Very large differences among 8 leading candidates:
~30 x in terms of area (Grain v1 vs. Edon80)
~500 x in terms of the throughput to area ratio
(Trivium (x64) vs. Pomaranch)

32. Your Project 14 SHA-3 candidates left in the contest Given: Generate:
specification of the function
reference implementation in C
interface
testbench (without test vectors)
Generate:
synthesizable code in VHDL
results for Xilinx FPGAs
optimized versions of the code
results for multiple families of FPGAs

33. All Projects - Organization
Projects divided into phases
Deliverables for each phase submitted through Blackboard at selected checkpoints and evaluated by the instructor and/or TA
Feedback provided to students on a best effort basis
Final report and codes submitted using Blackboard
at the end of the semester

34. Honor Code Rules
All students are expected to write and debug their codes individually
Students are encouraged to help and support each other in all problems related to the - operation of the CAD tools, - basic understanding of the problem.

35. Course Objectives At the end of this course you should be able to:
Code in VHDL for synthesis
Decompose a digital system into a controller (FSM) and datapath, and code accordingly
Write VHDL testbenches
Synthesize and implement digital systems on FPGAs
Understand behavioral, non-synthesizable VHDL and its role in modern design
Effectively code digital systems for cryptography, signal processing, and microprocessor applications
This knowledge will come about through homework, exams, and an extensive project
The project in particular will help you know VHDL and the FPGA design flow from beginning to end

36. The Engineering Building, Room 3204
Hands-On Sessions
Wednesday, September 9, 2009
The Engineering Building, Room 3204
Group 1: 4:30-7:10pm
Group 2: 7:20-10:00pm