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L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,

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Presentation on theme: "L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,"— Presentation transcript:

1 L12 – VHDL Overview

2 VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU2

3 Overview  HDL – Hardware Description Language A language that allows description of hardware for documentation, simulation, synthesis, verification, …  To use an HDL you need a CAD system that supports it.  Major CAD systems support VHDL, Verilog, System C, System Verilog  CAD systems (just some of them) Cadence – Incisive Mentor Graphics (Model Sim) – ModelSim, Questa Altera, XILINX (have arrangement to use ModelSim) Synopsis – Mainly toward synthesis and ASIC production from HDL descriptions 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU3

4 A brief history of HDLs  The development of today’s HDL began in 1980. State of CAD – generators and proprietary HDLs VHDL requirements set in 1981 VHDL IEEE 1 st standard in 1987 – New versions in 1993, 1997, 2000, 2002, 2008. And a new version is being worked on.  Verilog 1 st standard was in 1995  System C 1 st standard was in 2005  System Verilog merged with Verilog in 2009. New version in 2012. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU4

5 Common to all systems  Have source HDL file  Structure of generated files is common  Library files are  for design units 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU5

6 A First Example  Desire to do a VHDL description of a full adder.  A device consists of An Interface An operational part  Interface – The INPUTS AND OUTPUTS  Operational Part – The FUNCTIONAL BEHAVIOR 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU6

7 VHDL Entity Design Unit  Format ENTITY unit_name IS [port_clause] END unit_name;  For a full adder would have: ENTITY full_adder IS PORT(a,b,cin : IN bit; sum : OUT bit; cout : OUT bit); END full_adder;  The PORT portion is termed a Port Clause When specified in the port clause these signals have scope over all architectures of this entity 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU7

8 Signals/Port Modes/Types  PORT(a,b,cin:IN bit; sum:OUT bit; cout: OUT bit);  Signals: Names referenced in the Port Clause are signals. A,b,cin,sum,cout represent wires of the physical unit. SIGNALS are objects that have both a value and a time component.  Port Modes: In this example you have inputs and outputs. The Port Mode specifies the direction of the signal transfer and a couple of other properties of the port. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU8

9 Signals/Port Modes/Types  Modes: IN – signal can only be used (i.e., can only be read or can only be used on the right-hand-side of an equation). CANNOT BE ASSIGNED TO!! OUT – signal value can only be written. Cannot be seen or used in the design as it is an output and therefore external. INOUT – signal can be both written to (assigned to) and read (used). However, signals of thie type are connected to busses and therefore this signal mode requires the signal to be resolved. BUFFER – signal value can be written to and used internally in the design. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU9

10 Basic Types  Built in – part of the standard and the language proper.  TYPE BIT – your typical binary type with values of ‘0’ and ‘1’. Declaration that established this type  TYPE BIT is (‘0’, ‘1’); Use of SIGNALS of TYPE bit a <= ‘0’; b <= x AND y OR z;  Note that the value is either ‘0’ or ‘1’ 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU10

11 Architectural Design Unit  Specifies the operational part ARCHITECTURE identifier OF entity_id IS [declarations] BEGIN [architecture_statement_part] END [identifier]; [architecture_statement_part] – Any concurrent statement of the language 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU11

12 Example of Architecture  For a full adder ARCHITECTURE one OF full_adder IS BEGIN sum <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END one;  This style of description is referred to as a dataflow description. It is excellent for the combinational logic leaf units of a design. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU12

13 Consider a 4 bit Adder  This hardware is to modeled in VHDL  First will do a dataflow model for the unit as a whole. Will create two alternative dataflow models.  Then will create a structural model where the leaf units are basic gates. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU13

14 A Multibit Adder Example  Will model using a dataflow style Bit Vectors for ports and individual signals internally Bit Vectors for ports and bit vectors internally  The Entity Design Unit (same for both) ENTITY mb_adder IS PORT(a,b : IN bit_vector(3 downto 0); cin : IN bit; cout : OUT bit; sum : OUT bit_vector(3 downto 0)); END mb_adder; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU14

15 The first dataflow Architecture  ARCHITECTURE one OF mb_adder IS  SIGNAL c : BIT_VECTOR (4 downto 0);  BEGIN  c(0) <= cin;  sum(0) <= a(0) XOR b(0) XOR c(0);  sum(1) <= a(1) XOR b(1) XOR c(1);  sum(2) <= a(2) XOR b(2) XOR c(2);  sum(3) <= a(3) XOR b(3) XOR c(3);  c(1) <= (a(0) AND b(0)) OR (a(0) AND c(0)) OR  (b(0) AND c(0));  c(2) <= (a(1) AND b(1)) OR (a(1) AND c(1)) OR  (b(1) AND c(1));  c(3) <= (a(2) AND b(2)) OR (a(2) AND c(2)) OR  (b(2) AND c(2));  c(4) <= (a(3) AND b(3)) OR (a(3) AND c(3)) OR  (b(3) AND c(3));  Cout <= c(4);  END one; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU15

16 Dataflow Architectures  Dataflow architectures should be limited to leaf units.  The level of complexity should be limited.  The 4 bit adder is not overbearing but much more than this should be avoided.  Probably want to limit dataflow descriptions to 30 or so lines.  Dataflow architectures synthesize extremely well across most synthesis tools (Altera, Xilinx, Synopsis, Mentor Graphics) 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU16

17 The Second Dataflow Architecture ARCHITECTURE two OF mb_adder IS SIGNAL c : BIT_VECTOR (4 downto 0); BEGIN c(0) <= cin; sum <= a XOR b XOR c(3 downto 0); c(4 downto 1) <= (a(3 downto 0) AND b(3 downto 0)) OR (a(3 downto 0) AND c(3 downto 0)) OR (b(3 downto 0) AND c(3 downto 0)); Cout <= c(4); END two;  Note the power of this HDL specification  The Carry ripples through repeated evaluations of the equation as whenever a signal on the right-hand-side changes, the equation is re-evaluated and a new value scheduled for assignment to the signal.  Also synthesizes well. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU17

18 Operations on Type BIT  Consider the following declaration SIGNAL x,y : bit;  Logical Operations x AND y Also have shift operations x OR y arithmetic shifts ASR ASL x NAND y x NOR y logical shifts LSR LSL x XOR y x XNOR y these work on vectors NOT y  NOTE: For logical expressions the equation is only evaluated until the result is determined. 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU18

19 Assignment and Relational Operators  Assignment Operators For signal <= For variables :=  Relational Operators (x=y) (x/=y) (x =y) Example of use (x=‘1’) AND (y=‘0’) 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU19

20 VHDL Structural Example  Again consider the full adder  Before doing a structural description must have the components that are going to be wired together. These must first be written and compiled into the library.  Only the ENTITIES are given. Each would have an architecture. ENTITY and2 IS PORT (A,B : IN BIT; Z : OUT BIT); END and2;  ENTITY xor2 IS PORT (A,B : IN BIT; Z : OUT BIT); END xor;  ENTITY or3 IS PORT (A,B,C : IN BIT; Z : OUT BIT); END or3 ; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU20

21 The AND and OR gates  AND 2 ENTITY and2 IS PORT (A,B : IN BIT; Z : OUT BIT); END and2; ARCHITECTURE one OF and2 IS BEGIN Z <= A and B AFTER 2 ns; END one;  OR3 ENTITY or3 IS PORT (A,B,C : IN BIT; Z ; OUT BIT); END or3; ARCHITECTURE one OF or3 IS BEGIN Z <= A or B or C AFTER 2 ns; END one; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU21

22 Structural Example for a full adder  The first part ARCHITECTURE structural OF full_adder IS -- Must declare the components that are to be used COMPONENT and2 PORT (A,B : IN BIT; Z : OUT BIT); END COMPONENT ; COMPONENT xor2 PORT (A,B : IN BIT; Z : OUT BIT); END COMPONENT ; COMPONENT or3 PORT (A,B,C : IN BIT; Z : OUT BIT); END COMPONENT ; -- State which library to find them in and which architecture to use. FOR ALL : and2 USE ENTITY WORK.and2(behavioral); FOR ALL : xor2 USE ENTITY WORK.xor2(behavioral); FOR ALL : or3 USE ENTITY WORK.or3(behavioral); -- Declare local signals required. SIGNAL addt. ct1, ct2, ct3 : BIT; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU22

23 The second part of the Architecture  From the BEGIN BEGIN -- Wire up XOR gates for a XOR b XOR cin G1:xor2 PORT MAP(a,b,addt); G2:xor2 PORT MAP(addt, cin, sum); -- Wire up the cout function. G3:and2 PORT MAP(a,b,ct1); G4:and2 PORT MAP(a,cin,ct2); G5:and2 PORT MAP(b,cin,ct3); G6:or3 PORT MAP(ct1,ct2,ct3,cout); END Structural; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU23

24 Multibit adder  Can use the structural full adder to wire up a multibit adder  The ENTITY Design Unit ENTITY mb_adder IS PORT (a,b : IN BIT_VECTOR(3 downto 0); cin : IN BIT; cout : OUT BIT; sum: OUT BIT_VECTOR(3 downto 0)); END mb_adder;  Entity is the same as before 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU24

25 The multibit Architecture  ARCHITECTURE structural OF mb_adder IS  -- Must declare the components that are to be used  COMPONENT full_adder  PORT( a,b,cin : IN BIT;  sum : OUT BIT;  cout : OUT BIT);  END COMPONENT;  FOR ALL : full_adder USE ENTITY work.full_adder(structural);  SIGNAL ic1,ic2,ic3 BIT;  BEGIN  U0: full_adder(a(0),b(0),cin,sum(0),ic1):  U1: full_adder(a(1),b(1),ic1,sum(1),ic2):  U2: full_adder(a(2),b(2),ic2,sum(2),ic3):  U3: full_adder(a(3),b(3),ic3,sum(3),cout):  END structural; 1/8/2007 - L2 VHDL Introcution © Copyright 2012 - Joanne DeGroat, ECE, OSU25

26 Lecture summary  A note on VHDL styles: The dataflow style synthesizes well. The structural style synthesizes well.  Have seen several initial examples of VHDL code.  Will now focus on that part of the language for small dataflow and state machine designs.  Pick a problem 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU26

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