1. Chapter 2 – Transistors – Part 2 Field Effect Transistors (Unipolar Transistors) (Charge carriers: either electrons or holes)

2. Bipolar Transistor Electrons and holes are crossing emitter junction

3. 1) Field-effect transistors were invented by Julius Edgar Lilienfeld (Jewish Austro-Hungarian physicist) in 1925 and by Oskar Heil (German electrical engineer and inventor) in 1934.Julius Edgar LilienfeldOskar Heil 2)Practical devices were not able to be made until 1952 (the JFET). 3) Commonly used for weak-signal amplification. 4)Two types of FETs are : n-channel and p-channel FET. Field Effect transistor (FET) (or Unipolar transistors )

4. 5)The FET is a three terminal device i.e. the source (S), drain (D), and gate (G). 6)Source 6)Source : Provides the source of charge carriers (electrons/holes) for the channel current ( equivalent to Emitter in Transistor). Drain 7) Drain : The place where the charge carriers are removed ( or “drained”) from the device ( equivalent to Collector in Transistor).. 8)Gate 8)Gate : Controls the current flow in the channel ( equivalent to Base in Transistor).

5. 9) In both n-channel and p-channel, the charge carriers always flow from the source connection to the drain connection. 10) In n-channel, charge carriers are electrons. 11) In p-channel, charge carriers are holes.

6. n-channel FET

8. p-channel FET

9. Major Application – Display Driving Circuit

10. FET – Fabrication and Operation (reverse- biased)

12. n-channel FET

13. 1) Only one carrier type is involved in charge flow. 2)The charge flow is due to drift (as diffusion current small). 3)The voltage applied to the gate (reverse-biased) controls the current flowing in the source-drain channel. 4) No current flows through the gate electrode. Thus the gate is essentially insulated from the source-drain channel.

14. 6) Near the Drain end of the Gate : (i) Width of channel narrowest and (ii) junction width is widest. 7) Because here the reserve bias is the sum of Gate potential (V gs ) and the Drain potential (V ds ). 8) Nonuniform voltage drop along the channel and nonlinear variation in channel width make the exact analysis complicated.

15. Drain Current, I d voltage pinch off is actually for a given –V GS any increase in V DS will not cause further increases in drain current. If drain current stops this is V GS OFF which is of the same magnitude as pinch off but opposite polarity voltage e.g. V GS off = - 5 pinch off voltage = +5 V on the transfer characteristic curve. (pinch off voltage) (pinch of) pinch off = 핀치 끄기 Pinch = 핀치

16. Expression for drain current in saturation region. Vgs > Vp and Vds = Vgs – Vp Drain current in the active region Vds ≥ Vgs - Vp

17. active region Drain current saturation occurs when the Vds equals the Vgs minus the Vp (pinch off voltage). The value of the saturated drain current, I D is then given by the above equation. n-channel FET

18. 1. Reverse Bias voltage near the drain end of the gate terminal - No drain current Reverse Potential = V gs (Gate potential) + V ds (Drain potential) If -3V (V gs ) and (10) (V ds ), then Reverse Potental = -13V or magnitude of Reverse Bias between p- and n-types is 13V Drain current I d = ? Case 1: If reverse voltage at the bottle neck = -14V, Drain current I d = ? Case 2: If reverse voltage at the bottle neck = -12V, Drain current I d = ? Bottle neck Reverse Bias pn junction diode (fixed) (varied)

19. I d is proportional to - 2. Drain current I d is proportional to V gs - V p due to pinchoff. V p = -3V for n-channel FET - Case 1: V gs = -4 V, the V gs - V p = -4 V – (-3V) = - 1.0V - Case 2: V gs = -3 V, the V gs - V p = -3 V – (-3V) = 0V - Case 3: V gs = -2 V, the V gs - V p = -2 V – (-3V) = +1.0V - Case 4: V gs = -1 V, the V gs - V p = -1 V – (-3V) = +2.0V - Case 5: V gs = 0 V, the V gs - V p = -0 V – (-3V) = + 3.0V - Case 5: V gs = 1 V, the V gs - V p = 1 V – (-3V) = + 4.0V (fixed) (varied) Drain current I d Increases

20. 3. Additional reserve voltage, - V ds / 2 Reverse Bias voltage

21. Exercise : 1 For n-channel FET I d = I dss (1 – V gs / V p )2, V p = - 3.0 V Find I d (i)V gs = -2, -1, and 1V (ii)V gs = 0 V If I d = 0 mA, V gs = ?

22. N-channel FET – Biasing n-channel FET

23. 1)The input impedance of the FET is extremely large (in the range of 10 10 –10 15 Ω). 2)With a positive voltage on the drain, with respect to the source, electron current flows from source to drain through the CHANNEL. 3)If the gate is made negative with respect to the source, an electrostatic field is created, which squeezes the channel (i.e. channel width is reduced) and reduces the current. 4) Signal voltages applied to the gate result in corresponding variations in drain current.

24. n-channel FET

25. The physical meaning of this term ( I dss ) leads to one definition of pinch-off voltage, V P, which is the value of V ds (drain-source voltage) at which the maximum I dss flows. Another definition of pinch-off voltage

26. Current-voltage characteristics ( or collector characteristics) p-channel FET V ds (V) I d (mA) V ds (V) I d (mA) V ds (V) I d (mA) V ds (V) I d (mA) 0----0 0 0 5 5 5 5 10----10----10----10---- 15----15----15----15---- 20----20----20----20---- V gs = - 0.5VV gs = 0 V V gs = 0.5V V gs = 1.0 V Gate is reversed biased.

27. Operation : Current – voltage characteristics of p-channel FET - - --

28. The Transfer Characteristics The transfer characteristic for a JFET can be determined experimentally, (i)keep drain-source voltage, V ds constant, and (ii) determine drain current, I d for various values of gate-source voltage, V gs.

29. For p-channel FET When V gs = V P with V ds = 0 (we get using V p = V gs + V ds ), the two depletion layers touch over the entire channel length and the whole channel is closed.

30. i)Characteristcs shows the variation of I d with V gs. ii) I dss denote the drain current with shorted gate. iii) The curve extends on both sides i.e. V gs can be negative as well as positive. iv) Since V gs can be positive also I dss is not maximum value of drain current. v) Characteristics shows square law dependence ( I d  V 2 gs ). vi) Transfer characteristics is an alternative way of describing the nonlinear electrical properties of the FET.

31. For n-channel FET