1. Virtual Memory

2. Virtual Memory: Topics Why virtual memory? Virtual to physical address translation Page Table Translation Lookaside Buffer (TLB)

3. Another View of Memory Hierarchy Regs L2 Cache Memory Disk Tape Instructions, Operands Blocks Pages Files Upper Level Lower Level Faster Larger Cache Blocks Thus far { Next: Virtual Memory {

4. Why Virtual Memory? Today computers run multiple processes, each with its own address space Too expensive to dedicate a full-address- space worth of memory for each process Principle of Locality –allows caches to offer speed of cache memory with size of DRAM memory –DRAM can act as a “cache” for secondary storage (disk)  Virtual Memory Virtual memory – divides physical memory into blocks and allocate them to different processes

5. Mapping Virtual to Physical Memory Program with 4 pages (A, B, C, D) Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”) Physical MemoryVirtual Memory A B C D D A B C 0 4 KB 8 KB 12 KB 0 4 KB 8 KB 12 KB 16 KB 20 KB 24 KB 28 KB Disk

6. Virtual Memory Terminology Virtual Address –address used by the programmer; CPU produces virtual addresses Virtual Address Space –collection of such addresses Memory (Physical or Real) Address –address of word in physical memory Memory mapping or address translation –process of virtual to physical address translation More on terminology –Page or Segment  Block –Page Fault or Address Fault  Miss

7. Program operates in its virtual address space HW mapping Physical memory (incl. caches) virtual address (inst. fetch load, store) physical address (inst. fetch load, store) Virtual to Physical Addr. Translation Each program operates in its own virtual address space Each is protected from the other OS can decide where each goes in memory Combination of HW + SW provides virtual  physical mapping

8. Use table lookup (“Page Table”) for mappings: Virtual Page number is index Virtual Memory Mapping Function –Physical Offset = Virtual Offset –Physical Page Number (P.P.N. or “Page frame”) = PageTable[Virtual Page Number] Virtual Memory Mapping Function Virtual Page No. OffsetPhys. Page No. Offset translation Virtual Address Physical Address 31... 109... 0 29... 109... 0

9. Address Mapping: Page Table Virtual Address: virtual page no.offset index into Page Table Physical Address Page Table Valid Access Rights Physical Page Number... Page Table Base Reg physical page no. offset

10. Page Table Entry (PTE) Format Valid bit indicates if page is in memory –OS maps to disk if Not Valid (V = 0) Contains mappings for every possible virtual page If valid, also check if have permission to use page: Access Rights (A.R.) may be Read Only, Read/Write, Executable P.T.E. V.A.R.P.P.T. ValidAccess RightsPhysical Page Number V.A.R.P.P.T....... Page Table

11. Typical TLB Format Tag: Portion of virtual address Data: Physical Page number Dirty: since use write back, need to know whether or not to write page to disk when replaced Ref: Used to help calculate LRU on replacement Valid: Entry is valid Access rights: R (read permission), W (write perm.) Virtual Addr.Physical Addr. DirtyRefValidAccess Rights

12. Translation Look-Aside Buffers TLBs usually small, typically 128 - 256 entries Like any other cache, the TLB can be fully associative, set associative, or direct mapped VA Processor PA TLB Lookup Cache Main Memory miss hit Data hit miss Translation

13. The Big Picture TLB access TLB hit? Virtual address try to read from PT page fault? replace page from disk TLB miss stall No Yes Write? try to read from cache Cache hit? No Yes Set in TLB cache/buffer mem. write Deliver data to CPU cache miss stall Yes No Yes

14. 14 Translation Look-Aside Buffers TLB is usually small, typically 32-4,096 entries Like any other cache, the TLB can be fully associative, set associative, or direct mapped Processor TLBCache Main Memory miss hit data hit miss Disk Memory OS Fault Handler page fault/ protection violation Page Table data virtual addr. physical addr.

15. Valid Tag Data Page offset Page offset Virtual page number Physical page numberValid 1220 20 16 14 Cache index 32 Data Cache hit 2 Byte offset Dirty Tag TLB hit Physical page number Physical address tag 31 30 29 15 14 13 12 11 10 9 8 3 2 1 0 DECStation 3100/ MIPS R2000 Virtual Address TLB Cache 64 entries, fully associative Physical Address 16K entries, direct mapped

16. Parallel Address translation (TLB and Cache access) Example: L1-8K, L2-4M, Page-8K, cl- 64B, VA-64b, PA-41b

17. Things to Remember Apply Principle of Locality Recursively Manage memory to disk? Treat as cache –Included protection as bonus, now critical –Use Page Table of mappings vs. tag/data in cache Spatial locality means Working Set of pages is all that must be in memory for process to run Virtual memory to Physical Memory Translation too slow? –Add a cache of Virtual to Physical Address Translations, called a TLB Need more compact representation to reduce memory size cost of simple 1-level page table (especially 32  64-bit address)