1. Comp Sci 251 -- pipelining 1 Ch. 13 Pipelining

2. Comp Sci 251 -- pipelining 2 Pipelining

3. Comp Sci 251 -- pipelining 3 Performance of Pipeline One instruction completes every clock cycle n stages in pipeline  up to n times faster speedup < n because some instructions do not need every stage Note: individual instructions are not faster

4. Comp Sci 251 -- pipelining 4 MIPS Pipeline 5 stages IF: instruction fetch ID: instruction decode (read registers) EX: instruction execution, address calc MEM: memory access WB: write back (to register)

5. Comp Sci 251 -- pipelining 5 Implementing a single-cycle pipeline IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB Every stage takes the same time, whether there is work or not Each stage must be stretched to accommodate the slowest instruction

6. Comp Sci 251 -- pipelining 6 Total time for each instruction Instr Fetch Reg ReadALU Operation Data access Register Write Total Time Load word (lw) 200 ps100 ps200 ps 100 ps800 ps Store word (sw) 200 ps100 ps200 ps 700 ps R-format (add, sub, and, or, slt) 200 ps100 ps200 ps100 ps600 ps Branch (beq) 200 ps100 ps200 ps500 ps

7. Comp Sci 251 -- pipelining 7 Single-cycle non-pipelined execution IRRALUMEMR IRRALUMEMR lw $7, 100($5) lw $8, 200($5) lw $9, 300($5) IR 800 ps 3 independent lw instructions will take 3 x 800 ps = 2400 ps

8. Comp Sci 251 -- pipelining 8 Pipelined execution IF ALUMEM RR R ALUMEM R ALUMEM R R 200 400 600 800 1000 1200 1400 lw $7, 100($5) lw $8, 200($5) lw $9, 300($5) 200ps 3 independent lw instructions takes 3 x 200 ps = 600 ps 4 times faster than the single-cycle non-pipelined execution

9. Comp Sci 251 -- pipelining 9 Pipeline Hazards Control Hazards caused by conditional branch instruction cannot decide which instruction is next until stage 3 (or stage 2 with beefed up processor) pipeline wants to start next instruction during stage 2

10. Comp Sci 251 -- pipelining 10 Solutions to Control Hazards Stall: – start next instruction during stage 3 (assume branch is resolved in stage 2) – equivalent to placing a “nop” after every branch Predict: – if incorrect, flush the bad instruction – Some prediction strategies assume all branches not taken static: assume some always taken, others never taken dynamic: use past history, keep stats on branches

11. Comp Sci 251 -- pipelining 11 Solutions to Control Hazards Delayed decision: (used in MIPS and SPARC) – instruction following branch always executes – branch takes place after this instruction – compiler or assembler fills “delay slots” with useful instructions (or nop’s) Change order of neighboring instructions, if logically acceptable Or nop

12. Comp Sci 251 -- pipelining 12 Data Hazards Assume register write happens in WB stage add $s0, $t0, $t1 sub $t2, $s0, $t3 Example requires three pipeline stalls – too costly to allow – too frequent for compiler to resolve

13. Comp Sci 251 -- pipelining 13 Solution to Data Hazards Forwarding: getting the missing item early from internal resources sub gets $s0 value from ALU, not reg. file sometimes forwarding avoids stalls

14. Comp Sci 251 -- pipelining 14 Solution to Data Hazards sometimes forwarding only reduces stalls

15. Comp Sci 251 -- pipelining 15 Advanced Pipelining Techniques Superpipelining: large number of stages Superscalar – multiple copies of each stage – several instructions started/finished per cycle

16. Comp Sci 251 -- pipelining 16 Advanced Pipelining Techniques Dynamic Pipeline Scheduling

17. Comp Sci 251 -- pipelining 17 Pentium Pro / Power PC 604