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Spring 2006 1 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Advanced Computer Architecture Lecture 16 Cache design example Data/tag.

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Presentation on theme: "Spring 2006 1 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Advanced Computer Architecture Lecture 16 Cache design example Data/tag."— Presentation transcript:

1 Spring 2006 1 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Advanced Computer Architecture Lecture 16 Cache design example Data/tag Controller

2 Spring 2006 2 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Cache design example CPU: B2Logic model Memory –256 x 8, RAM (no ROM) –4X slower then cache, Rdy signal Cache: direct mapped, write-through –Data: 16 x 8, RAM (no delay) –Tag: 16 x 4 RAM (no delay)

3 Spring 2006 3 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering System schematic

4 Spring 2006 4 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering General memory design Main Cache Control Driver enable R/W# hit System Bus

5 Spring 2006 5 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Memory system schematic

6 Spring 2006 6 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering RAM schematic G1 initiates a memory operation Rdy indicates access time complete

7 Spring 2006 7 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Cache block diagram Trw# Crw# Data Address Hit A D in D out A 4 8 4 8 4 D in 4 R/W# 16 x 4 tag 16 x 8 cache low high low R/W# Match 4 high

8 Spring 2006 8 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Cache schematic tag data

9 Spring 2006 9 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Controller description Read hit: read cache data and drive it onto bus Write hit: write data/tag into cache and data into memory Read miss: read data from memory, drive it onto bus, write data/tag into cache Write miss: same as write hit (we will use this fact later in the design)

10 Spring 2006 10 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering State diagram 000 c bd Ready Write ReadHit ReadMiss Ready Reset Missing outputs

11 Spring 2006 11 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find states? a = 000, idle b = 001, write c = 010, read hit d = 100, read miss

12 Spring 2006 12 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find next state table? ReadWriteHitRdyPSNS 0000aa 1ab 11ac 10ad 1ba 0bb ca 1da 0dd Wr RdHit RdMiss

13 Spring 2006 13 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find output table? StateAckCbenCrw#MbenMrw#Mg1 0Idle001010 bWriteRdy00001 cRdHit111010 dRdMissRdy00111

14 Spring 2006 14 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Complete state diagram? 000 Ready Write ReadHit ReadMiss Ready Reset

15 Spring 2006 15 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Controller schematic

16 Spring 2006 16 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Program Write to memory –Address: 0x00, 0x10, 0x20, 0x30 –Data: 0x11, 0x22, 0x33, 0x44 Read misses, hits

17 Spring 2006 17 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find controller states? InstructionAccessState 60011Write-hit1 61022Write-miss1 62033Write miss1 63044Write miss1 53000Read hit2 52000Read miss4 52000Read hit2 51000Read miss4 51000Read hit2 50000Read miss4 50000Read hit2

18 Spring 2006 18 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Sample trace

19 Spring 2006 19 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Sample trace, continued.

20 Spring 2006 20 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering

21 Spring 2006 21 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find states? b = 001, write c = 010, read hit d = 100, read miss

22 Spring 2006 22 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find next state table? ReadWriteHitRdyPSNS 0000aa 1ab 11ac 10ad 1ba 0bb ca 1da 0dd Wr RdHit RdMiss

23 Spring 2006 23 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find output table? StateAckCbenCrw#MbenMrw#Mg1 0Idle001010 bWriteRdy00001 cRdHit111011 dRdMissRdy00111

24 Spring 2006 24 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Complete state diagram? 000 010 001100 Ready Write ReadHit ReadMiss Ready Ack Mrw# Crw# Cben Mben Ack=Ready Reset Crw#

25 Spring 2006 25 EE 437 Lillevik 437s06-l16 University of Portland School of Engineering Find controller states? InstructionAccessState 60011Write1 61022Write1 62033Write1 63044Write1 53000Read Hit2 52000Read Miss4 52000Read Hit2 51000Read Miss4 51000Read Hit2 50000Read Miss4 50000Read Hit2

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