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Trigger Interface and Distribution J. William Gu Jefferson Lab 1. What is TID 2. TID Structure and functions 3. Possible usage in the system 4. TID related.

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Presentation on theme: "Trigger Interface and Distribution J. William Gu Jefferson Lab 1. What is TID 2. TID Structure and functions 3. Possible usage in the system 4. TID related."— Presentation transcript:

1 Trigger Interface and Distribution J. William Gu Jefferson Lab 1. What is TID 2. TID Structure and functions 3. Possible usage in the system 4. TID related boards (Mezz and FANIO) 5. Status

2 11/13/2015 J. W. GU, Data Acquisition Group 2 1. What is TID Trigger Interface (TI) + trigger Distribution (TD) = TID TID has some Trigger Supervisor functions TSTS SDSD TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID VMEVME CTPCTP TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD CTPCTP TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD Upto 127 front end crates 11/13/20152

3 J. W. GU, Data Acquisition Group 3 2. TID Structure and functions Optical IO HFBR-7924 #1,#2,#3,#4, #5,#6,#7,#8 TrgSv Rev. 2 interface External I/O (trg, clk…) VME  PROM (FPGA firmware) Emergency/remote re-programming VXS P0 TD mode: from SD TI/TS mode: to SD VME 64x One dedicated link for redundant data collection Trg/Clk/Syc outputs On row_C Xilinx Virtex-5 LX30T-FG665 11/13/20153

4 J. W. GU, Data Acquisition Group 4 2. TID Structure and functions P0_SD_CLK_IN MC100LVEP111 TID_SELECT CLK250_1 HFBR_1 CLK2AD SyncCLK HFBR_8 HFBR_7 HFBR_6 HFBR_5 HFBR_4 HFBR_3 HFBR_2 AD9510 ON_NB4N840 & SY55857 CLK250_2 CLK125 ASEL[1:0] BSEL[1:0] P0_CLKA P0_CLKB P0_CLKC P0_CLKD MC100EP57 CLK2_in CLK2AD External_In CLK_OSC SUBSYS_CLK TS_CLK CLKFPGAR CLK250_3 CLK_FREQ1 CLK3125 CLK_FREQ2 CLKSEL[1:0] SY58607 CLKFPGA CLK250_P2 CLKTDC_P2 CLKTDC CLKADC_P2 CLKADC 2.1 Clock Distribution CLK1_in 11/13/20154

5 J. W. GU, Data Acquisition Group 5 2. TID Structure and functions FPGA Front Panel Mezz. (Rev2) MC100LVEP14 SY58607ADN2805P0 MC100LVEP14 SD_TRG_IN FPGA_TRIG_1 GTP#1_TX GTP#5_TX GTP#3_TX TS2_TRG_IN Ex_TRG_IN GTP#1_RX GTP#5_RX HFBR#5 HFBR#6 HFBR#7 HFBR#8 HFBR#2 HFBR#3 HFBR#4 TRG1B F1_TRG FADC_TRG TRG1A P2_TRG1 HFBR#1 Sel1 Sel3 Sel2 2.2 TD mode, trigger fanout 11/13/20155

6 J. W. GU, Data Acquisition Group 6 2. TID Structure and functions HFBR-7934 #1 RX TX FPGA XC5VLX30T MC100EP14 HFBR-7934 #4 RX TX HFBR-7934 #5 RX TX HFBR-7934 #8 RX TX MC100EP14 MC100EP11 TS_SD_P0_FAN_IN GTP#8 GTP#1 GTP#4 GTP#5 GTP#2 GTP#3 GTP#6 GTP#7 TRIG1 TRIG2 WARNING/BUSY GTP connection details : All the eight fibers are connected to the FPGA, they are status input and trigger output in TD mode; and trigger input and status output in TI mode. (different FPGA firmware) 11/13/20156

7 J. W. GU, Data Acquisition Group 7 2. TID Structure and functions I_delay Encoding Manchester decoding Sync decoding Manchester encoding O_delay Mux TD_CLKSYNC FPGA Ext_Sync P0_CLKSYNC MC100LVEP111 MC100EP14 SEL P0_SyncA HFBR7924#1 P0_SyncB P2_Sync FP_Sync1 FP_Sync2 HFBR7924#8 HFBR7924#2 2.3 Sync signal distribution The encoding/decoding is implemented in the FPGA, synchronized to the 250MHz clock 11/13/20157

8 J. W. GU, Data Acquisition Group 8 2. TID Structure and functions Trigger synchronization on trigger interface using SYNC signal A FIFO (built in the FPGA) is used to compensate for the DES. latency T-WORD 12 WORD 0 T-WORD 14T-WORD 13 Ser Fiber 1T HFBR Fiber nT HFBR FIFO 1 Des. Fiber nR HFBR Fiber 1R HFBR Des. FIFO n WORD 1 WORD 0WORD 1 WORD 4WORD 5WORD 2WORD 3 WORD 4WORD 2WORD 3 WORD 7WORD 8 WORD 5 WORD 6 WORD 7WORD 8 WORD 6 WORD 10WORD 11 WORD 9 11/13/20158

9 J. W. GU, Data Acquisition Group 9 2. TID Structure and functions The front panel will look like the drawing at the right. There are eight optical transceivers in TD mode, and one (or two) optical transceivers plus copper cable connectors in TI mode. 2.4 Front panel: (always available TM ) VME remote loading firmware; Serial links to switch slot#A, switch slot#B; Potential fast data link to SD; 2.5 Other features: 11/13/20159

10 J. W. GU, Data Acquisition Group 10 3. Possible usage in the system 3.1 Standard experiment setup: This is the same content drawing as in page 2 TSSD TID1TID1 T I D 16 TID2TID2 TI D1 TI D2 TI D8 SD ADC/TDC BUSY Trg/Clk/Sync BUSY Up to 16 Up to 8 Global Trigger Distribution Crate Front End Readout Crate TID Boards One Distribution Crate; Up to 127 Front End Crate, Plus the global trigger crate. 11/13/201510

11 11/13/2015 J. W. GU, Data Acquisition Group 11 3. Possible usage in the system SDSD TID/TSTID/TS ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC Front End Crates Up to 8 crates 3.2 Commissioning/testing setup (or a small DAQ system) Up to 9 (front end) crates in total TID as TI (this crate) and TD (up to 8 other crates) with TS function Front End Crate 11/13/201511

12 11/13/2015 J. W. GU, Data Acquisition Group 12 3. Possible usage in the system TSTS SDSD TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID TIDTID VMEVME SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC TID/TSTID/TS ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC SDSD TIDTID ADC/TDCADC/TDC VMEVME ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC TID/TSTID/TS ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC ADC/TDCADC/TDC Global Distribution Crate Front End Crates Up to 8 crates Up to 16 T I Ds One global distribution crate, Up to 127 front end crates One TID/TS per subsystem with Up to 8 crates (It is not required for the subsystem to have its global inputs from the same T I D) 3.3 Luxury option: parallel subsystem and global control; doubling the number of optical transceivers (expensive) 11/13/201512

13 11/13/2015 J. W. GU, Data Acquisition Group 13 4. TID related boards (Mezz and FANIO) 4.1 Mezzanine board for TS_Rev2 interface Same connector and jumpers, same component (different package type) as TI_rev2 board; With the Mezzanine board, this TID will behave like a TI_Rev2 board, to work with TS_rev2. Board size: 2¼” x 3¼” How many mezz. Boards do we need? _____ 11/13/201513

14 11/13/2015 J. W. GU, Data Acquisition Group 14 4. TID related boards (Mezz and FANIO) 4.2 Fan out board (VME sized board) for CAEN 1290 TDC #1 #5 #2 #6 #3 #7 #4 #8 #9 #13 #10 #14 #11 #15 #12 #16 It fans out the TRIGGER, CLOCK (41.7MHz), RESET signals; It merges the BUSY signals (OR); It communicates with VME P2 connectors (with TI D ); It supports up to 16 CAEN TDCs; One 64-pin cable (on FANIO board)  four 16-pin cables (on CAEN 1290) How many fanout boards do we need? ________ 11/13/201514

15 11/13/2015 J. W. GU, Data Acquisition Group 15 4 pieces are manufactured, two PCBs are being assembled; Board test starts next week 5. Status 11/13/201515

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