1. Chapter 6 (I) Designing Combinational Logic Circuits Static CMOS
EE141
Chapter 6 (I)
Designing Combinational Logic Circuits
Static CMOS
Pass Transistor Logic
V1.0 4/25/2003
V1.1 5/2/2003
V2.0 5/4/2003

2. Revision Chronicle
5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide.
5/4:
Add 4 Pass-Transistor Logic Slides from Weste textbook
Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic

3. Combinational vs. Sequential Logic
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Combinational vs. Sequential Logic
Combinational
Sequential
Output = f ( In )
Output = f (
In, Previous In )

4. Static CMOS Circuits V or
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Static CMOS Circuits
At every point in time (except during the switching transients) each gate output is connected to either
via a low-resistive path (PUN, PDN)
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring the transient effects during switching periods).
This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. V DD or ss

5. Static Complementary CMOS
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Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1
In2
InN
PUN
PDN
PMOS only
(good for transfer 1)
NMOS only
(good for transfer 0) …
One and only one of the networks (PUN or PDN) is conducting in steady state
Pull-up Network (PUN) and Pull-down Network (PDN)
are Dual Logic Networks

6. Threshold Drops in NMOS and PMOS -- Check Candidates for PUN and PDN
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Threshold Drops in NMOS and PMOS -- Check Candidates for PUN and PDN
VDD
VDD
PUN S D G
VDD G D S
0  VDD
0  VDD - VTn
VGS CL CL
PDN
VDD  0
VDD  |VTp|
Why PMOS in PUN and NMOS in PDN … threshold drop
NMOS transistors produce strong zeros; PMOS transistors generate strong ones
VGS CL CL D S
VDD G G S D

7. Complementary CMOS Logic Style
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Complementary CMOS Logic Style

8. NMOS Transistors in Series/Parallel Connection
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high

9. PMOS Transistors in Series/Parallel Connection
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PMOS Transistors in Series/Parallel Connection

10. EE141
Example 1: NAND2 Gate
(Use DeMorgan’s Law)

11. EE141
Example2: NOR2 Gate

12. Design of Complex CMOS Gate
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Design of Complex CMOS Gate B C A D A
Shown synthesis of pull up from pull down structure D B C

13. Constructing a Complex Gate
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Constructing a Complex Gate
SN2
SN1
SN2
SN1

14. Static CMOS Properties
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Static CMOS Properties
Full rail-to-rail swing: High noise margins
Logic levels not dependent upon the relative device sizes: Ratioless
Always a path to Vdd or GND in steady state: Low output impedance
Extremely high input resistance; nearly zero steady-state input current (input to CMOS gate)
No steady-state direct path between power and ground: No static power dissipation
Propagation delay function of output load capacitance and resistance of transistors

15. Switch Delay Model Req A A B Rp A Rn CL Cint CL B Rn A Rp Cint A Rp A
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Switch Delay Model
Req A A B Rp A Rn CL
Cint CL B Rn A Rp
Cint A Rp A Rp A Rn CL
Note capacitance on the internal node – due to the source grain of the two fets in series and the overlap gate capacitances of the two fets in series
NOR2
INV
NAND2

16. Input Pattern Effects on Delay
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Input Pattern Effects on Delay
Delay is dependent on the pattern of input (Assume Rp = 2 Rn for same size of transistors)
Low-to-high transition:
Both inputs go low
Delay is 0.69 (Rp/2) CL
One input goes low
Delay is 0.69 (Rp) CL
High-to-low transition:
Both inputs go high (required for NAND)
Delay is 0.69 (2Rn)CL A Rp B Rp CL Rn B Rn
Cint A

17. Transistor Sizing NAND is preferred than NOR implementation!!
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Transistor Sizing
Assumes Rp = 2Rn at same W/L A Rp B Rp B Rp A Rn CL
Cint 4 2 CL Rn 2 A B Rn
Cint
Assumes Rp = Rn 1
NAND is preferred than NOR implementation!!

18. Delay Dependence on Input Patterns
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Delay Dependence on Input Patterns
NAND2 is true
OUT connects to GND
Input Data
Pattern
Delay
(psec)
A=B=01 69
A=1, B=01 62
A= 01, B=1 50
A=B=10 35
A=1, B=10 76
A= 10, B=1 57
A=B=10
A=10, B=1
Voltage [V]
A=1, B=10
Gate sizing should result in approximately equal worst case rise and fall times.
Reason for difference in the last two delays is due to internal node capacitance of the pulldown stack. When A transitions, the pullup only has to charge CL; when A=1 and B transitions pullup have to charge up both CL and Cint.
For high to low transitions (first three cases) delay depends on state of internal node. Worst case happens when internal node is charged up to VDD – VTn.
Conclusions: Estimates of delay can be fairly complex – have to consider internal node capacitances and the data patterns.
time [ps]
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
A=1, B=10 (for both Cint and CL)
A=1, B=01 (Consider Body effect)

19. Transistor Sizing a Complex CMOS Gate
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Transistor Sizing a Complex CMOS Gate A B 8 4 C 8 D 4
OUT = D + A • (B + C)
For class lecture.
Red sizing assuming Rp = Rn
Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3
Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output)
Green for symmetric response and for performance (where Rn = 3 Rp)
Sizing rules of thumb
PMOS = 3 * NMOS
1 in series = 1
2 in series = 2
3 in series = 3
etc. A 2 D 1 B 2 C 2

20. Fan-In Considerations
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Fan-In Considerations
4-input
NAND Gate
While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND
C1, C2, C3 on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS
CL of 3.2 fF with no output load (all diffusion capacitance – intrinsic capacitance of the gate itself).
To give a 80.3 psec tpHL (simulated as 86 psec)

21. Fan-In ConsiderationsB A CL C3 C2 C1
Distributed RC model
(Elmore delay)
tpHL = 0.69(R1C1+(R1+R2)C2
+ (R1+R2+R3)C3
+ (R1+R2+R3+R4)CL
=0.69 Reqn(C1+2C2+3C3+4CL) R4 R3 R2 R1
Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case.

22. tp as a Function of Fan-In
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tp as a Function of Fan-In
tpHL
Quadratic (H->L) tp
tp (psec)
tpLH
(L  H)
Linear Increase in
Intrinsic Capacitance,
Assume Only one
PMOS is On for critical
case
Fixed fan-out (NMOS 0.5 micrcon, PMOS 1.5 micron)
tpLH increases linearly due to the linearly increasing value of the diffusion capacitance
tpHL increase quadratically due to the simultaneous incrase in pull-down resistance and internal capacitance
fan-in

23. (tpHL, tpLH) as a Function of Fan-Out
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(tpHL, tpLH) as a Function of Fan-Out
slope is a function of the driving strength
Gates with a fan-in greater than or equal to 4 becomes
excessively slow and should be avoided!

24. tp as a Function of Fan-In and Fan-Out
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tp as a Function of Fan-In and Fan-Out
Fan-in: quadratic due to increasing resistance and capacitance
Fan-out: each additional fan-out gate adds two gate capacitances to CL To the preceding stage)
a1 term is for parallel chain, a2 term is for serial chain, a3 is fan-out

25. Fast Complex Gates: Design Technique 1
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Fast Complex Gates: Design Technique 1
Transistor sizing
Increase Intrinsic parasitic cap and create CL of the preceding stage
Progressive sizing CL
Distributed RC line:
M1 > M2 > M3 > … > MN
(the FET closest to the
output is the smallest)
Not simple in Layout!
InN MN C3
M1 have to carry the discharge current from M2, M3, … MN and CL so make it the largest
MN only has to discharge the current from MN (no internal capacitances)
In3 M3 C2
In2 M2 C1
In1 M1

26. Fast Complex Gates: Design Technique 1

27. Fast Complex Gates: Design Technique 2
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Fast Complex Gates: Design Technique 2
Input reordering: Put late arrival signal near the output node.
critical path
critical path
01 CL CL
charged
charged 1
In1
In3 M3 M3 1 C2 1 C2
In2
In2 M2
discharged M2
charged 1 C1 C1
In3
discharged
For lecture.
Critical input is latest arriving signal
Place latest arriving signal (critical path) closest to the output
In1
charged M1 M1
01
Delay determined by time to discharge CL, C1 and C2
Delay determined by time to discharge CL

28. Fast Complex Gates: Design Technique 3
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Fast Complex Gates: Design Technique 3
Logic Restructuring
(A)
F =NAND8 Gate
Reduced fan-in -> deeper logic depth
Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuration).
Only simulation will tell which of the last two configurations is faster, lower power
(C)
(B)
In general, C > B > A in speed

29. Design Technique 3: Logic Restructuring
Tradeoff between Area and Speed
(and Power?)
(from Neil Weste, 2nd Ed, 93)

30. Fast Complex Gates: Design Technique 4
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Fast Complex Gates: Design Technique 4
Isolating fan-in from fan-out using buffer insertion CL CL
Reduce CL on large fan-in gates, especially for large CL, and size the inverters progressively to handle the CL more effectively

31. Fast Complex Gates: Layout Technique
(A): 4 internal cap
2 output diff cap
(B): 4 internal cap
4 output diff cap
(A) Is better than (B)
(A)
(B)

32. Optimizing Performance in Combinational Networks
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Optimizing Performance in Combinational Networks CL In
Out 1 2 N
(in units of tinv)
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4
How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed?

33. EE141
Logical Effort
Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current
Logical effort increases with the gate complexity

34. EE141
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
g = 1
g = 4/3
g = 5/3

35. EE141
Logical Effort
From Sutherland, Sproull

36. Estimated Intrinsic Delay Factor

37. Logical Effort p – intrinsic delay : gate parameter
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Logical Effort
p – intrinsic delay : gate parameter
g – logical effort : gate parameter
f – effective fanout
Normalize everything to an inverter:
ginv =1, pinv = 1
Divide everything by tinv
(everything is measured in unit delays tinv)
Assume g = 1.

38. Delay in a Logic Gates Gate delay: d = h + p Effort delay
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Delay in a Logic Gates
Gate delay:
d = h + p
Effort delay
Intrinsic delay
Effort delay:
h = g f
Logical Effort
Effective fanout = Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size

39. Logical Effort of Gates

40. Logical Effort of Gates
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Logical Effort of Gates t
pNAND
g = 4/3
p = 2
d = (4/3)f+2
pINV t
Normalized delay (d)
g = 1
p = 1
d = f+1
F(Fan-in) 1 2 3 4 5 6 7
Fan-out (f)

41. EE141
Add Branching Effort
Branching effort:

42. Multistage Networks Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Sdi = Spi + Shi

43. Optimum Effort per Stage
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Optimum Effort per Stage
When each stage bears the same effort:
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage:
Minimum path delay

44. Optimal Number of Stages
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Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
Substitute ‘best stage effort’

45. Example: Optimize Path
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Example: Optimize Path
g = 1 f = a
g = 5/3 f = b/a
g = 5/3 f = c/b
g = 1 f = 5/c
Effective fanout, F = 5
G = 25/9
H = GF=125/9 = 13.9
h = 1.93 (optimal stage effort) =
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59

46. EE141
Example – 8-input AND

47. Method of Logical Effort
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Method of Logical Effort
Compute the path effort: F = GBH
Find the best number of stages N ~ log4F
Compute the stage effort f = F1/N
Sketch the path with this number of stages
Work either from either end, find sizes: Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

48. EE141
Summary
Sutherland,
Sproull
Harris

49. Pass-Transistor Logic

50. Pass-Transistor Logic
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Pass-Transistor Logic

51. Pass Transistor Logic Basics
Logic Function:
Example: AND Gate
A, B: A is Input signal, B is the Control Signal

52. Example: Design of XNOR2
(a) Truth table
(b) Pass-network
Karnaugh map
A as the control signals
B as the passed signals
(c) Logic function

53. Example: Implementation of XNOR2
Transmission Gate (b)NMOS (c)Cross-couple

54. Example2: Construct Boolean Functions
Truth Table:
Implement:

55. NMOS-Only Logic Suffer from Vt degradation Body effect (Vsb has value)
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NMOS-Only Logic
3.0 In
Out
[V]
2.0 x e g a l t o V
1.0
0.0
0.5 1
1.5 2
Suffer from
Vt degradation
Body effect (Vsb has value)
Time [ns]

56. NMOS-only Switch V does not pull up to 2.5V, but 2.5V - V
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NMOS-only Switch
C =
2.5 V
C =
2.5 V M 2
A =
2.5 V
A =
2.5 V B M B n C M 1 L V
does not pull up to 2.5V, but 2.5V - V B TN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)

57. NMOS Only Logic: Level Restoring Transistor
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NMOS Only Logic: Level Restoring Transistor V DD
Level Restorer V DD M r B M 2 X A M n
Out M 1
Advantage: Full Swing
Restorer adds capacitance, takes away pull down current at X
Ratio problem among (Mr and Mn)

58. Restorer Sizing Upper limit on restorer size
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Restorer Sizing
100
200
300
400
500
0.0
1.0
2.0 W / L r
=1.0/0.25
=1.25/0.25
=1.50/0.25
=1.75/0.25 V o l t a g e
[V]
Time [ps]
3.0
Upper limit on restorer size
Pass-transistor pull-down can have several transistors
in stack

59. Solution 2: Single Transistor Pass Gate with VT=0
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Solution 2: Single Transistor Pass Gate with VT=0 V DD V DD 0V
2.5V V 0V
Out DD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS

60. Complementary/Differential Pass Transistor Logic (CPL/DPL)
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Complementary/Differential Pass Transistor Logic (CPL/DPL)

61. Solution 3: Use of Transmission Gate
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Solution 3: Use of Transmission Gate C C A B A B C C
C =
2.5 V
A =
2.5 V B C L C
= 0 V

62. Resistance of Transmission Gate
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Resistance of Transmission Gate

63. Application1: Inverting 2-to-1 Multiplexer
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Application1: Inverting 2-to-1 Multiplexer
GND
VDD A B S F

64. Application2: 6-T(ransistor) XOR Gate
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Application2: 6-T(ransistor) XOR Gate
Truth Table A B F M1 M2
M3/M4 B A F 1
B=0: Pass A Signal
B=1: Inverting A Signal

65. Application3: Transmission Gate Full Adder
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Application3: Transmission Gate Full Adder
Similar delays for Sum and Carry

66. Delay in Transmission Gate Networks
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Delay in Transmission Gate Networks V
n-1 n C
2.5 In 1 i
i+1 V 1
i-1 C
2.5 i
i+1 R eq C
(a)
(b) m R eq R eq R eq In C C C C
(c)

67. EE141
Delay Optimization