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Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Published byThomasina Morrison Modified over 9 years ago

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Presentation on theme: "Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share."— Presentation transcript:

1 Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains. Transistors in parallel do not share source/drains. If layout was available, actual capacitances would be extracted from layout. Three-input Nand Gate

2 Gate Delay: 3-input NAND Driving 4X Inverter

3 Gate Delay: Worst case TPHL (fall time), TPLH (rise time) TPHL TPLH

4 Gate Delay: Best case TPHL (fall time), TPLH (rise time) Best Case TPLH = R/3*(9C+12C) = R/3 * 21C = 7RC Best Case TPHL = Worst Case TPHL because all transistors in series.

5 Compute Elmore Delay for the following gate, best/worst TPLH/TPHL

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