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Actel RTAX-S FPGA Reliability Summary Kangsen Huey, HiRel Program Manager Ravi Pragasam, Senior Marketing Manager
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 2 Agenda : RTAX-S Introduction Qualification MIL-PRF-38535, Class Q Actel Antifuse Reliability Studies EAQ ( Enhanced Antifuse Qualification) HSB (High Single S, Single B) Design New Processes and Procedures ELA : Enhanced Lot Acceptance XSEM : Die Cross Sections at Antifuse Reliability Data and FIT Rate Summary Actel Flash Product Roadmap
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 3 RTAX-S Product Lineup Introduced in 2004 and QML class Q level Qualified in 2005 Wafers fabricated on 0.15 µm process at United Microelectronics Corp (UMC), Taiwan Releasing in 2007
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 4 RTAX-S New Technology Features First Antifuse FPGA that offers up to 4 Million system gates with enhanced features: Embedded RAM blocks Extensive I/O standard support Hardened charge pump, clock trees, Power On Reset circuit TMR Flip Flops RTAX-S Antifuse Technology Implemented with 0.15 μm CMOS process with new circuits designed to improve programming current and reduce net loading Antifuse is similar in structure, but thinner than RTSX-SU generation due to the lower programming voltage Results in less distance for material transport of the plate material during programming, resulting in better I PEAK tolerance for net loading Single S-Antifuses get 67% less I PEAK stress during switching compared to RTSX-SU Designer software has SAL (S- Antifuse Loading) to dramatically reduce Single S-Antifuse count Single B-Antifuses have 50% less I PEAK vs. RTSX-SU Architecture includes adding buffers to reduce net loading on long nets Programming Current B, I, S, K antifuses have 10% to 20% more programming current
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 5 RTAX-S QML Qualification with Enhanced Testing for Antifuse RTAX-S QUALIFICATION MIL-PRF-38535, Class Q Qualification Actel Antifuse Reliability Studies (Enhanced Antifuse Qualification + HSB) &
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 6 RTAX-S Qualification (1/3) MIL-PRF-38535, Class Q Level Compliant Qualification Qualification Burn In (QBI) Design was developed for qualification life test Tests the overall CMOS and Antifuse technology Maximizes resources utilization like the Flip Flops, IOs, SRAM, FIFO, Carry chains, etc. Functional test vector developed to for 3-temp FT Uses fully class Q level screened devices Group C test 87 RTAX2000S and 98 RTAX1000S devices passed 1,000 hours of group C at 125 o C Pass/Fail criteria tightened to LTPD(3) equivalent of 129(1) of the largest RTAX2000S devices Assuming every 2 RTAX1000S equals to one RTAX2000S Added LTOL (Low Temp Operating Life) test 78 RTAX1000S devices passed 1,000 hours of LTOL at -55 o C Group A, B, D, ESD, Latch-Up, IO Capacitance also performed 6 parts (2 RTAX2000S and 4 RTAX1000S) in Group C and 1 part in LTOL failed due to equipment failures FA reports available upon request
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 7 RTAX-S Qualification (2/3) EAQ (Enhanced Antifuse Qualification) Objective is to uncover antifuse failure modes and determine antifuse failure rate Uses highly perceptive and stressful designs for antifuse evaluation Similar to the antifuse studies employed for RTSX-SU The EAQ design is capable to detect small (pico to nano seconds) shifts in net propagation delay, which can be detected through analyzing the delta delays High and Low Temperature Operating Life tests (HTOL/LTOL) performed with RTAX1000S-CG624 devices 291 units passed 1,000 hours of HTOL at +125 o C and 250 hours of LTOL at -55 o C One unit had CMOS process related failure (non-antifuse related) after 500 hours of HTOL 6 units failed due to equipment (BIB data contention) Devices did not go through the Burn-In screening required for QML class Q level devices 120 units carried on and all passed 6,000 hours of HTOL with No failures
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 8 RTAX-S Qualification (3/3) High single S-Antifuse and high single B- Antifuse (HSB) utilization design Testing was conducted after the completion of QML qualification activity HSB design maximized the utilization of both single S-Antifuse and single B-Antifuse High and Low Temperature Operating Life tests (HTOL/LTOL) performed with RTAX1000S-CG624 devices 298 units passed 1,000 hours of HTOL at +125 o C and 250 hours of LTOL at -55 o C Two units had CMOS failure due to electrical over-stress (non-antifuse related) at 250 hours pull point of HTOL Devices did not go through the Burn-In screening required for QML class Q level devices
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 9 RTAX-S Qualification Designs Design utilization for QBI, EAQ and HSB Reliability Testing Qualification designs represent the worst case end-use condition User designs have generally less utilization than the above qualification designs
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 10 Antifuse Usage Statistics The EAQ and HSB designs were created to study specific Antifuse types like: The Critical K-Antifuse Single S-Antifuse Single B-Antifuse Number of critical antifuses utilized in the various RTAX1000S Reliability Test Vehicles NO antifuse faults have been observed in RTAX1000S-CG624 reliability studies with these designs
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 11 RTAX-S Production Process Enhancement RTAXS Wafer specific XSEM Standard Quality Control Monitor Extended Lot Acceptance (ELA)Standard B, E Flow processing Actel Specific E-test Thermal Runaway Characterization XY Programming New Process StepsOld Process Steps
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 12 RTAX-S Processes and Procedures (1/2) Standard Quality Control Monitor (QCM) Programming & functional test using LTPD 30 (8 samples, 0 failures) Design is identical to QBI (targeted for general CMOS/Antifuses) Test is done per assembly build for the RTAX250S Extended Lot Acceptance (ELA) Test is done per wafer lot 168 hours of burn in at 125 ºC with stringent EAQ design Sample size: RTAX250S – 100 units RTAX1000S – 24 units RTAX2000S – 14 units Wafer lot acceptance criteria allows Zero antifuse related failures If any failures or outliers are detected, failure analysis is performed to determine root cause XY Programming Wafer number and die location on wafer is now programmed into each unit during wafer sort Silicon Sculptor Programming SW revision also programmed into device at final design programming
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 13 RTAX-S Processes and Procedures (2/2) Wafer-specific cross section inspection (XSEM) Two samples per wafer are cross-sectioned at antifuses XSEMs are inspected for anomalous antifuse construction Wafers are scrapped if found to be beyond the specification Susceptible wafers are required to be used as ELA samples All the wafers that pass are built for shipments Thermal Runaway Characterization This test is required per wafer lot (starting with 2007 fab out lots) 2 sample units are programmed with ELA design and characterized at oven temperature of 125 o C, 130 o C, and 135 o C Lots that exhibit thermal run-away phenomena are scrapped Actel E-test In addition to wafer foundry provided E-test data, Actel runs additional E-test after wafers arrive Provides more in depth information on antifuse related parameters
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 14 RTAX-S Reliability FIT Rate NO Antifuse faults have been observed to date in any of the reliability testing (QBI, EAQ, ELA, HSB) thus far 1.7 Million device hours have been accumulated to date Refer http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf for details (updated as needed)http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf Failure rate estimation: Device FIT = 11.7 @ Tj = 55 ºC Using the chi-square distribution and a minimum upper confidence limit of 60% per JESD74 CMOS Activation Energy: Ea = 0.7 eV Includes 1 CMOS process related failure The remaining failures were identified as EOS or equipment related FA reports available upon request
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 15 RTAX-S On-Going Quality and Reliability Improvement Process Change Notification through GIDEP Problem Advisory SC7-P-06-01 (PCN0608), Elimination of RTAX-S ICCA Current Increase Due to Heavy Ion-Induced Upset SC7-P-06-02 (PCN0606), EDAC Macro modification to correct simultaneous reads and writes occur to a single address. SC7-P-07-02 (PCN0625), to correct routed clock timing under- estimation All issues were associated with software bugs and discovered through internal and customer failure analysis Silicon has remained the same since qualification On-Going Process Improvement After Qualification X-Y Programming, Thermal Run-Away Analysis High Frequency SET, High Temperature SEL, Prompt Dose Completed ESD Testing
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 16 RTAX-S Reliability Summary Actel has enhanced its Qualification Procedure to include both MIL-PRF-38535 QML-Q and Enhanced Antifuse Qualification (EAQ) New processes have been implemented to ensure high quality and highly reliable RTAX-S product is shipped NO antifuse failures detected with almost 1.7M device-hours of testing which showcases robustness of this technology Parts have been baselined in many programs Has started to develop QML class V level qualification/certification with the RTAX4000S qualification process
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 17 Planning to Fly RTAX-S MUOSAdvanced EHFNPOESSGalileo Lunar Reconnaissance Orbiter James Webb Space Telescope Mars Science Lab Bepi Colombo GOES-R GAIA
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© 2007 Actel Confidential and ProprietaryHuey/Pragasam January 2007New Technology Insertion Workshop 18 New Technology Plans: Space-Flight Flash FPGAs Actel continues to develop new technology for Space applications such as Flash based FPGAs Unique Flash advantages Non-Volatile and Live at Power-Up Reprogrammable RTA3PE (130nm) Based on the commercial Flash product line Radiation projections – suitable for LEO / short duration payloads Immune to SEL TID to ~ 15 to 20 Krad, parametric and functional To implement Soft TMR for protection against data SEUs Flight units expected 2008 to 2009 Mil-Std-883 qualified RT-G4 (90nm) Project founded by DTRA In architecture concept phase Expect flight units 2010 to 2012 Target TID to 300 Krad 5M to 10M system gates
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