1. PADS Power Aware Distributed Systems Architecture Approaches USC Information Sciences Institute Brian Schott, Bob Parker UCLA Mani Srivastava Rockwell Science Center Victor Lin and Charles Chien (PI)

2. Objectives Reconfigurable power-aware communications  Dynamically adapt communication processing during runtime based on channel condition and mission requirements.  Monitor channel conditions, including SNR, BER, RSSI, CIR, and Doppler shift.  Provide a library of run-time reconfigurable communication modules implemented in a high-level language such as JHDL.  Provide configuration control and monitor to middleware for power-aware protocols, allowing adaptation to be not only at the lower layers and below but also at the higher layer e.g. link and network. Proposed approach  Provides adaptation inclusive of the physical layer and supports adaptation at the higher protocol layer (e.g. routing).  Utilizes reconfigurable technology (e.g. FPGA).  Adapts not only digital processing (100X power dynamic range) but also analog processing (10-20X power dynamic range).

3. Reconfigurable Radio Architecture Switch or Duplexer RF Frontend ~ Reconfiguration Interface D/A A/D Digital Processing FPGA + DSP  P or FSM Memory Power & Bandwidth Fc Bandwidth & Rolloff Rate Resolution, Modulation & Spreading Up Conversion Down Conversion Many Tunable Parameters to Obtain Large Dynamic Range in Power Savings

4. Reconfigurable Parameters Runtime reconfigurable baseband (100X power dynamic range)  Adjustable Data rates: 8, 16, 32, 64 Kbps and 1 Mbps  Direct-sequence spread-spectrum modem (selectable processing gain 12, 15, 18, 21 dB)  FEC coder/encoder: convolutional codes (on/off).  Un-equalized QAM, including BPSK and QPSK. Reconfigurable analog processing (10-20X power dynamic range)  Adapt the receive bandwidth, spanning a range of 10 kHz to 1 MHz.  Configures mode of power amplifier (Class A and E/F).  Transmit power control (13 dB range minimum)  Adapt the sampling rate of the ADC and DAC (100 Ksps to 4 Msps)

5. Reconfigurable Baseband Architecture Many modules in the architecture. Not all are needed at same time. Reconfigure to save power!

6. Power Breakdown (Modem) Additional processing can be implemented for higher dynamic range (e.g. interleaving) Total dynamic range is less due to overhead  Quiescent Power is fixed

7. Transceiver Implementation (preliminary)

8. Power Breakdown (RF) Preliminary Total RF Power (Maximum)  685 mW (RX)  1.1 W (TX, 20 dBm)

9. Detailed Power Dissipation for FPGA Modem Estimated Power for an Xilinx Virtex FPGA Quiescent and IO Power Not Included Possible Dynamic Range (spread/unspread) = 2 mW to 165 mW (80x)

10. FPGA Reconfiguration  Xilinx Virtex parts have partial reconfiguration capabilities.  SelectMAP™ Interface - 8-bit interface for loading configuration data.  Partial Reconfiguration – allows changing the functionality of a circuit without disrupting its operation or completely reconfiguring the FPGA.  Data Rate – based on the SA-1110 running at 200MHz and one access cycle taking 20 clocks, the data rate for loading configuration data will be 10 Mbytes/sec.

11. VCC Xilinx TestBed FPGA XV300 Prototype Area Clock Generation Pushbuttons And DIP switches LEDS

12. Baseband Test Setup Pattern Generator Logic Analyzer I Q TX Modem RX Modem Clock Generator Power Supply with Current Meter Power Supply with Current Meter Data_In Data_Out Debug

13. Logic Analyzer Output

14. Plans  FY01 (Q3): FPGA modem prototypes  - Direct-sequence spread-spectrum (8 kbps, 16 kbps, 32 kbps, 64 kbps)  - Programmable system clock (1 MHz – 16 MHz)  - S-Map interface  - Coded convolutional encoder/decoder  FY01 (Q4): FPGA modem prototypes with communication modules.  - Integrate FEC with modem  - Narrowband mode  FY02 (Q2): FPGA radio prototypes with run-time reconfiguration support and baseline RF module.  FY03 (Q1): FPGA radio with RF amplifier and BW adaptive analog interface.  FY03 (Q3): Deployment platform with technology from the research platform.

15. Technology Transfer  Implement a deployable platform based on technology instrumented on the research platform.  Power-aware OS scheduler  Power-aware network protocols  Power-aware reconfigurable radio  Demonstrate PACC technology in DoD applications  SensIT  Situation awareness in MOUT scenarios  Self-healing minefield  Ship-board automation RSC’s Highly Deployable Remote Access (HiDRA: hidra.rsc.rockwell.com) Collins PLGR LAN provides situation awareness to individual soldiers.