1. Baeg, Sanghyeon Reliable & high Speed Computing Lab. Hanyang University

2. Objectives Implementation of Reliable and Low Power Sensor Node SoC Contents Sensor Network of Nodes Why Low Power and Reliability Researches Undergoing

4. Main components of sensor nodes Microcontroller Transceiver External memory Power source One or more sensors External Memory Sensors Micro Controller Communication device Communication device Power Source

5.  Energy is typically more limited in sensor networks than in other wireless networks because of the nature of the sensing devices and the difficulty in recharging their power sources.  Power consumption in the sensor node is for the Sensing, Communication and Data Processing.  Ex) monitoring or at detecting phenomena. Examples include office building environment control, wild-life habitat monitoring, etc.

6.  More energy is typically required for data co mmunication in sensor node. Energy expendit ure is less for sensing and data processing.  The energy cost of transmitting 1 Kb a distance of 100 m is approximately the same as that for the executing 3 million instructions by 100 millio n instructions per second/W processor LOW POWER!!

7.  IC should perform in accordance with expectations for a predetermined period.  Sudden death of sensor nodes cost replacing and management efforts.  Sensor nodes are typically exposed to extreme environmental situations such as temperature changes, weathers, animals.

8.  Mission critical sensor nodes needs high prob ability of surviving through self-guarding/ diagnosis features. RELIABILITY!!

9.  Power reduction for memories used in sensor network

10.  Research for cross talks in memory cells Increasing memory density and decreasing technology geometry  Increasing capacitive cross talks Reduced reliability because of additional power consumption and noise paths  Becomes the source of intermittent failure Crosstalk in marginal size is not detected by normal test  Increasing costs for test Test method using negative voltage stress  Testable method with low cost

11.  Analysis for High-speed Interface Issues

12.  Chip Schematic & Test Result

13.  Micro Processor(8051) as underlying uP  Implement Processor in FPGA as initial stage with reduced instruction for power saving FPGA MC8051_ALU SIU TMRCTR SIU CONTROL RAM (128X8) ROM (64KX8) RAM (64KX8)

14.  Customized IP Design is beneficial in low power design by reducing unnecessary capacitance in design.

15.  Equipment for development and testing  Logic Analyzer  Function Generator  BER Tester  Oscilloscope  Power Supply  FPGA Board for Development & Testing

16.  Chip Test Board(Interconnection Testing Board)  Memory Test Board

17.  In the second year of sensor hardware nodes  Focused on development in low power and reliable sensor node system  Currently focusing on IP development  Will be moving to FPGA system development  Eventually, single chip solution

18. Thanks