1. 1 Engineering issues for FPCCD VTX Detector Y. Sugimoto KEK July 24, 2007

2. 2 FPCCD 5  m pixel size, 15  m epi- layer Accumulate signal during a train and read out between trains Moderate readout speed ~10Mpix/s No power cycling Two wafers make a doublet, and three doublets make the detector Operate at low temperature ~220K  ladders are put inside a cryostat LayerR (mm) 120 222 332 434 548 650

3. 3 Readout channels One readout channel covers 128x13000(L1- L2)/128x20000(L3-L6) pixels For outer layers, larger pixel size may be acceptable and could be 128x13000 Wafer size (mm 2 )r.o. ch/wafer# of wafers# of r.o. channels L110x6516 15(  )x2(z) 480 L210x6516 15(  )x2(z) 480 L320x10032 16(  )x2(z) 1024 L420x10032 16(  )x2(z) 1024 L520x10032 24(  )x2(z) 1536 L620x10032 24(  )x2(z) 1536 Total2206080

4. 4 Engineering challenge Power consumption and cooling method Wafer thinning and the ladder design Installation method ….

5. 5 Power consumption Heat source Ohmic loss in gate electrode (probably negligible) CCD source follower and load resister Readout ASIC Clock driver CCD and ASIC must be inside the cryostat Clock driver may be put outside the cryostat Most of power is consumed by “drivers” No heat source in the image area Our R&D goal: Electronics: < 100 W in the cryostat Mechanics: Compatible with 100W

6. 6 Power consumption R&D status Sensor R&D First custom CCD in FY2007 4ch/chip, 4 different source follower designs Smallest power consuming channel: ~10mW/ch Readout ASIC Amp, CDS, and charge-sharing SAR ADC Design completed, submission in September 4ch/chip < 10mW/ch if output is not connected (driving 100  load with 1V pulse consumes ~10mW!)

7. 7 Wafer thinning Two methods are considered Partial thinning by etching (like DEPFET collab) Easy to handle More material (thick frame) Total thinning by etching or mechanical method Less material Hard to handle (wire bonding OK?) Flatness ?

8. 8 Partial thinning Sample CCDs; Front side processed 300  m thick frame and 20  m thick image area Flatness is poor  20  m looks too thin

9. 9 FEA of Ladders Si (CCD wafer) RVC (Reticulated Vitreous Carbon) 10 cm Epoxy Deformation by self-weight is calculated by FEA program COMSOL

10. 10 FEA of Ladders Parameters (assumption) Geometry Density (g/cm 3 )X0 (g/cm 2 )E (GPa) Si2.3321.8110 Epoxy1.1540.93 RVC0.0542.70.031 ThicknessWeightRadiation length Si 50  m 0.01165 g/cm 2 0.0534%X 0 Epoxy 50  m 0.00573 g/cm 2 0.014%X 0 RVC2 mm0.0084 g/cm 2 0.0234%X 0 Epoxy 50  m 0.00573 g/cm 2 0.014%X 0 Si 50  m 0.01165 g/cm 2 0.0534%X 0 Sum0.04316 g/cm 2 0.1582%X 0 0.08%X 0 /layer

11. 11 FEA of Ladders Results Maximum deformation: Without gap : v max =0.536  m With 0.2mm gap : v max =0.723  m For longer ladders v max ~ l 4  ~8.6  m for 20cm ladder without gap

12. 12 Summary and future prospect Among many engineering issues to be studied for FPCCD vertex detector, we have started study for Power consumption (sensor/ASIC R&D) Wafer thinning and ladder design Due to lack of resources, these studies are at very primitive stage As a long term goal (~2012?), construction of full size engineering model (dummy detector) would be necessary