1. Programmable Logic Training Course HDL Editor

2. HDL Entry Editor
The color coding enables the user to quickly enter the design
Text colored in red contains HDL key words, black contains user defined function and the green text represents comments

3. Language Assistant
The Language Assistant inserts templates of common functions into the design
Place the cursor at the location for the code to be entered
Open the Language Assistant by using the command Tools>Language Assistant or by clicking on its icon
Select the proper template and click on the Use button
Lines of text that begin with “- -” are comments

4. Synthesis Options Use the command Synthesis>Options Effort Level
Specifies the logic optimization effort
Optimize
Area produces a small netlist
Speed produces a fast netlist
Compile
Enables to the synthesized output to Macro level and Chip level compilation from Express
Show Constraint Editor
Enables to appear Constraint Editor after Synthesis

5. Programmable Logic Training Course State Editor

6. Create FSMs Graphically
Start by clicking on the State Editor icon
The Design Wizard creates the symbol for placement in schematic
Synthesizes FSM diagram into VHDL or ABEL code
HDL code is generated by the State Editor and can be viewed before synthesis

7. Creating State Machine (FSM)
To add states to the machine, click on the States icon
Name the states by double clicking on the default name inside the state symbol
Add Transitions between states by using its icon
The curve of the transition can be changed when it is added to the diagram
Add conditions for the transition by placing them on the transitions, using the Condition icon

8. After FSM Entry...
Generate the HDL code by using the command Synthesis>HDL Code Generation
The text file can be viewed if desired
Synthesize the logic using with the command Synthesis>Synthesize
Repair any warnings or messages that arise during compilation
Insert the symbol into the top-level schematic

9. Machine Properties
To open the Machine Properties dialog box, use the command FSM>Machines>Sreg0
The General template allows encoding the state machine
The user can also control which edge of the clock signal to use
Use One-hot encoding to improve the performance of large state machines
One-hot encoding uses more registers, but decreases the number of levels of logic

10. Programmable Logic Training Course Simulator

11. Waveform Viewer
To open the Simulator, click on the Functional Simulator or the Timing Simulator icons
An implementation within the Alliance M1 software must be completed before a Timing Simulation can be completed
Contains a list of input and output nodes and an area for viewing the signals generated by the simulator
The simulator is controlled by the Simulator Toolbox

12. Inserting Probes
Add probes in the schematic to automatically load a node into the Waveform Viewer
Click on the Probes icon and click on each node name in the schematic
The probes change color in the schematic to reflect their state

13. SC Probes Box
When the Insert Probes icon is selected in the Schematic Editor, the SC Probes box also opens. This box contains the following options:
Add Probes
Add Stimulators
Start the Simulator
Delete all probes
go to the previous event
go to the next event
Simulate one step
Save probes

14. Component Selector
Alternatively, open the Waveform Viewer, and enter nodes by using the Component Selector
Open the Component Selector by clicking on its icon in the Waveform Viewer

15. Stimulator Selector
Bc and NBc represent the normal and inverted outputs of a 16-bit counter
The square LEDs represent 16 user-defined formulas
The buttons labeled C1 - C4 represent user-defined clocks
The CS button is used with the graphical waveform editor to create a custom signal
To modify the clock frequency of the 16-bit counter, use the command Options>Preferences

16. Displaying Buses
To group signals, click on the MSB, hold the shift key, and click on the LSB. Then use the menu command Signal>Bus>Combine
To ungroup a bus, select the bus and use the menu command Signal>Bus>Flatten
To change the bus format, select the bus then use the menu command Signal>Bus>Display…
Any signals can be grouped within a bus

17. Programmable Logic Training Course Design Manager

18. Design Flow for Implementation
1. Invoke Design Manager
2. Start a Project or Open a Project
3. Specify Back Annotation File for Simulation
4. Implement the Design
5. Check Timing Results
6. Download the FPGA/CPLD

19. Step 1: Invoke Design Manager
Invoke the Design Manager
PC users: select icon
Command line usage: dsgnmgr
The Design Manager window appears:
Configurable Flow Engine
Controls start/stop points and custom options
Timing Analyzer
Report on net and path delays
PROM File Formatter
Create file to program configuration file into PROM
Hardware Debugger
Download configuration file
Design Editor
Device-level view of routing
Status Window

20. Step 1: Invoke Design Manager
Project
Versions
Revisions
Toolbox
Menu bar
Tool bar
Project
Directory containing netlists, also definition of family
Version
Based on a netlist of the design
New version is required when input design is changed
Revision
An implementation of a Xilinx netlist
Multiple revisions typically result from different options or part types

21. Step 2: Start a New Project
D. Use pull-down menu to
specify netlist format.
A. Select File -> New Project
B. Specify top level
input netlist
C. Specify working
directory

22. Step 2: Start a Project (cont.)
Set up the design for implementation
Select Part Type
A. Select Design -> Implement
B. Select Part
C. Select Options (...see next foil)

23. Step 3: Specify Back Annotation
Select Design -> Implement -> Options
Enable “Produce Timing Simulation Data”

24. Step 4: Implement the Design
Select Design -> Implement -> Run
Or press right arrow icon
“Run-only” Flow Engine appears
The design is implemented and the configuration file is created

25. Step 5. Check Results
Select Utilities -> Report Browser from the Design Manager
Reports are shown once available
Double-click to open
Yellow sparkles indicates new (not yet read)

26. Step 6: Configure the FPGA/CPLD
To configure, or program FPGAs, a bit file is downloaded
Configuration can be driven by a microprocessor
Data can be stored in a PROM
To configure CPLDs, a JTAG file is downloaded
CPLDs can be configured In-System, or
CPLDs can be configured using third party programmers
More information on Configuration is given later today