1. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting1 2009 ITRS Emerging Research Devices Working Group Face – to – Face Meeting Jim Hutchby – Facilitating Dolce La Hulpe Brussels Hotel 135, Chaussée de Bruxelles, 1310 La Hulpe, BEL Room – Mahogany (Near) Brussels, Belgium Wednesday, March 18, 2009 8:00 a.m. – 5:30 p.m.

2. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting2  Hiroyugi AkinagaAIST  Tetsuya AsaiHokkaido U.  Yuji AwanoFujitsu  George BourianoffIntel  Michel BrillouetCEA/LETI  Joe BrewerU. Florida  John CarruthersPSU  Ralph CavinSRC  An ChenAMD  U-In ChungSamsung  Byung Jin ChoKAIST  Sung Woong ChungHynix  Luigi ColomboTI  Shamik DasMitre  Erik DeBenedictisSNL  Simon Deleonibus LETI  Kristin De MeyerIMEC  Michael FrankAMD  Paul FranzonNCSU  Akira FujiwaraNTT  Christian GamratCEA  Mike GarnerIntel  Dan HammerstromPSU  Wilfried HaenschIBM  Tsuyoshi HasegawaNIMS  Shigenori HayashiMatsushita  Dan HerrSRC  Toshiro HiramotoU. Tokyo  Matsuo HidakaISTEK  Jim HutchbySRC  Adrian IonescuETH  Kohei ItohKeio U.  Kiyoshi KawabataRenesas Tech  Seiichiro KawamuraSelete  Rick KiehlU. Minn  Suhwan KimSeoul Nation U.  Hyoungjoon KimSamsung  Atsuhiro KinoshitaToshiba  Dae-Hong KoYonsei U.  Hiroshi KotakiSharp  Atsuhiro KinoshitaToshiba  Franz KreuplQimonda  Nety KrishnaAMAT  Zoran KrivokapicAMD  Phil KuekesHP  Jong-Ho LeeKyungpook Nation U.  Lou LomeIDA  Hiroshi MizutaU. Southampton  Fumiyuki NiheiNEC  Ferdinand PeperNICT  Yaw ObengNIST  Dave RobertsAir Products  Kaushal SinghAMAT  Sadas ShankarIntel  Atsushi ShiotaJSR Micro  Satoshi SugaharaTokyo Tech  Shin-ichi TakagiU. Tokyo  Ken UchidaToshiba  Yasuo WadaToyo U.  Rainer WaserRWTH A  Franz Widdershoven NXP  Jeff WelserNRI/IBM  Philip WongStanford U.  Kojiro YagamiSony  David YehSRC/TI  In-Seok YeoSamsung  In-K YooSAIT  Peter ZeitzoffFreescale  Yuegang ZhangLLLab  Victor ZhirnovSRC Emerging Research Devices Working Group

3. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting3  Review Administrative Aspects  Deliverables, Timeline, and Next Steps  Proposed Chapter Outline and Page Count/Allocation  Technology Entry Inclusion Criteria  Broadly inclusive  Maturity Metric (current publications)  Review Major Decisions  Hiramoto-san, U-In Chung, and Adrian Ionescu agree to serve as co-chairs of ERD with Jim Hutchby as chair.  Guiding Principles – In the 3 rd principle change “Novel Energy Transfer …” to “Novel Information Transfer…”  Begin to merge Memory technologies with Storage technologies in 2010.  Enter Carbon-based Nanoelectronics as a potential solution 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (1/3)

4. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting4  Decide Structure & Major Technical Entries for Memory, Logic and Architecture Sections  Factors considered  Structure  Content (particularly proposed numerical content) considering 1) Current experimental values, and 2) Long term potential values/goals for quantitative metrics  Decide Technology entries (drop/add/move to Transition Table)  Sections  Logic Devices (including relevant materials issues w/ ref. to ERM)  Memory Devices (including relevant materials issues w/ ref to ERM)  Emerging Research Architectures ( Decide approach for Architecture Section and build a strong connection between Logic & Architecture Sections). 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (2/3)

5. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting5  Review/critique each Technology Entry  Major barrier and/or weaknesses  Requirement(s) for new materials  Most important research questions to be addressed (materials and device structure)  Level of risk and anticipated maturation time  Decide Critical Assessment & Guiding Principle Sections  Critical Assessment  Memory  Logic  Guiding Principles – “Beyond CMOS”  Discuss Proposal for Highlighting Promising Options for Emerging Memory Technologies 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (3/3)

6. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting6 7:30Gathering time 8:00 Introductions 8:10Review meeting objectives and agenda Hutchby 8:20 Review of Administrative AspectsHutchby  Deliverables, Timeline, Events, & Next Steps  Chapter Outline, Page Count & Allocation  Cross TWG Linkages & Meetings 8:30Review/Discuss Status of Major Tech Sections  Section outline  Table structure (Row headers, etc.)  Table Content (Current & projected tables)  Key materials issues 8:30 Memory Devices Zhirnov 10:00Break ITRS ERD WG Meeting – March 18, 2009 Agenda

7. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting7 10:15 Logic Devices Bourianoff 11:45 MASTAR Readiness for III-V & Ge MOSFETsNg 12:00 Lunch 12:30 Emerging Research MaterialsGarner 1:30 ArchitecturesCavin 2:30 Discuss/Decide Difficult ChallengesHutchby 3:15 Discuss Evaluation & Guidance Sections  3:15 Critical AssessmentHutchby  3:45 Guiding PrinciplesHutchby 4:00Discuss Proposal for Highlighting Promising Hutchby Options for Emerging Memory Technologies 4:45 Review ERD/ERM Beyond CMOS IRC Pres.All 5:25Wrap up and Review Actions RequiredAll 5:30Adjourn ITRS ERD WG Meeting – March 18, 2009 Agenda

8. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting8 Draft ERD Chapter Outline  Scope (1 page)  Difficult Challenges (1)  Taxonomy Chart (1)  Devices  Memory Devices (13)  Logic Devices (15)  Architectures (10)  Critical Assessment (6)  Fundamental Guiding Principles (3)  Total Pages (50) DRAFT

9. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting9 Proposed 2009 ERD Working Group Organization ERD FunctionLeader u Chapter Chair – North AmericaHutchby u Chapter Co-chair – EuropeIonescu u Chapter Co-chair – Japan ERDHiramoto u Chapter Co-chair – Korea ERDChung u MemoryZhirnov u LogicBourianoff u ArchitectureCavin u Editorial TeamHutchby, Bourianoff, Cavin, Chung, Garner/Herr, Hiramoto, Ionescu, Zhirnov u ITRS Liaisons –PIDSNg, Hutchby –FEPColombo –Modeling & SimulationShankar/Das –MaterialsGarner –MetrologyHerr/Obeng –DesignYeh/Bourianoff –More than MooreBrillouet New in 2009

10. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting10 2009 ITRS/ERD Major Deliverables and Timeline ERD Chapter due August 21, 2009 Changed in San Francisco Major Tasks and Time Line  Outlines for Memory, Logic, Architecture, Mat’lMarch 18  Technology Requirements TablesJuly 1  Guiding Principles Section March 18  Draft Text Completed  Memory, Logic, Architecture, Material June 6  Functional Organization & Critical ReviewJuly 20  Scope, Difficult Challenges, etc.July 27  Chapter CompletedAugust 21  Chapter FrozenSept. 15 Major Face-to-Face Meetings in 2009  ITRS/ERD Meeting near Brussels, BelgiumMarch 18  ITRS/ERD Meeting at Semicon West (SF, CA)July 12  ERD/ERM Meeting at IEDM in WashingtonDec. 6  ITRS/ERD Meeting near Hsinchu, TaiwanDec. 13

11. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting11 Decisions for 2009 Chapter ♦ Memory –Include device structural aspects of the new NW PCRAM in ERD with a summary of the materials issues. Include more materials information in ERM on this topic. –Include the Spin Torque Transfer MRAM in ERD/ERM. –We will not include “Storage” technologies in 2009, but will begin to merge “Memory” and “Storage” technologies in 2010. At that time we will begin to include the “Magnetic Domain” or “Racetrack Memory” in ERD. –We will keep nanomechanical memory in ERD Memory Table. –Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table –Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory. –By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category. –Drop the Charge Trapping Memory as a Technology Entry – move to Transition Table? –Drop the Capacitive Memory Table

12. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting12 Decisions for 2009 Chapter ♦ Logic –We will have 3 Logic tables in 2009. They will be titled: Table 1: “MOSFET: Extending the Channel of MOSFETs to the End of the Roadmap” Table 2: “Non-Conventional FET, Charge-based Extended CMOS Devices” Table 3: “Non-FET, Non Charge-based ‘Beyond CMOS’ Devices” –ERD/ERM recommends carbon-based nanoelectronics to include CNT, graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon –Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues. –Seven potential technologies were considered: 1.Carbon-based Nanoelectronics 2.Collective spin 3.Spin torque transfer 4.Atomic and electrochemical metal 5.CMOL/FPNI 6.Single Electron Transistor 7.NEM S

13. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting13 Action Items (1/3) 1.Consider to include in the 2009 ERD Chapter the new chart entitled “Evolution of Extended CMOS” contributed by ERD Japan. BourianoffIn Process 2.Strengthen ties between US-EU-Asia. Requires good balance of representing members from three regions HutchbyIn Process 3.The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect. Bourianoff, ZhirnovDecided to not change; include note 4.Extend the Mission of ERD to include additional Research Vectors proposed by the Japan ERD WG. These are Numbers 1 – 4 listed in Item No. 1 above. BourianoffIPWGN Task 5.Consider moving to PIDS in 2009: 1) III-V Alternate Channel Materials, and 2) Low Dimensional Materials. Discuss this with PIDS. (This discussion has begun.) BourianoffIn Process 6.Make the mission of ERD clear. Make it more Globally justified.Hutchby 7. Organize an ERD Working Group in KoreaIn U. ChungCompleted

14. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting14 Action Items (2/3) 8.Bob Doering argued that the Critical Evaluation Chart gives the wrong message; a.We need to re-think this chart b.This chart assigns a different meaning to red than is used by all the other ITRS chapters. The other chapters use red to highlight a major research gap. c.We should point the directions into which “critical path” research should be directed. We need a way to distinguish a Fundamental Limit versus the Maturity of the Technology Entry HutchbyIn Process 9.Need a dialog with the Design and Systems Drivers ITWG to address synergy between the two chapters. Hutchby, Bourianoff, Yeh In Process 10.Discuss/decide upon expanding scope to include Sensors, Actuators, and Power Sources to encompass More than Moore or Functional Diversification Hutchby and Brillouet Decided to not do this in 2009 11.Discuss other materials (in addition to NiO) for Fuse/Anti-fuse Memory Tech Zhirnov & GarnerIn Process 12.Plan Memory FXF Meeting in Germany for April 2, 2008. Include Memory Expert Panel. ZhirnovDone 13.Write paper/proposal for NSF Funding for workshops.Hutchby/ZhirnovDone 14.Include Akinaga-san in Memory Working GroupZhirnovDone

15. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting15 # 1.Set up biweekly ERM/ERD editorial/driver team meetings (See proposed times for these meetings below) Hutchby 2.Discuss and create a draft of a STTRAM potential solution tableYeo and Yoda 3.Develop a process for reviewing Memory Technology Entries to present to the IRC for their direction regarding highlighting for more detailed roadmapping. Hutchby and ERD/ERM 3.Discuss Storage or Mass Memory Technology at SF Meeting. Korean ERD would like us to reconsider including Mass Memory/Storage in the ERD Chapter Hutchby 4.Continue discussions with PIDS regarding PIDS bringing STTMRAM into the PIDS chapter Hutchby 5.Set up bi-weekly TelecomsHutchby 6.Create a Potential Solution Table for STTMRAMBourianoff, Yeo, Chung 7.Dr. H. S. Hwang is a new Volunteer for the ERD Memory TeamChung 8.Dr. Ko will contribute to CNTs, III-V, GNR 9.Prepare recommendation regarding More than MooreBrillouetNov. 30 10,Discuss with Alan Allan the possibility of putting the Japanese ERD chart in the Executive Summary HutchbyMar. 18 11.Use colors in the ERD/ERM Critical Review that are consistent with the other chapters of the Roadmap Hutchby 12.Send to Mike Garner a reference to an IBM/Zurich paper on conformational change in molecules to modify tunnel barrier Waser 13.Update report on Molecular Devices – Discuss in Mar. 18 meetingWaser, ZhirnovMar. 18 Action Items (3/3)

16. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting16 Backup Slides

17. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting17 2009 ITRS Emerging Research Devices Editorial – Driver Team Meeting Charter and Scope George Bourianoff Mike Garner Jim Hutchby Victor Zhirnov Santa Clara, CA October 13, 2004 Edited December 10, 2006

18. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting18 Charter of ERD Chapter On behalf of the 2009 ITRS, develop an Emerging Research Devices chapter to --  Critically assess new approaches to Information Processing technology beyond ultimate CMOS  Identify most promising approach(es) to Information Processing technology to be implemented by 2024 To offer substantive guidance to –  Global research community  Relevant government agencies  Technology managers  Suppliers

19. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting19 Scope of ERD Chapter Integrated emerging research memory, logic and new architecture technologies enabled by supporting --  Materials and process technologies  Modeling and simulation  Metrologies Selection of specific technical approaches shall be  Guided by fundamental requirements  Bounded by ERD’s topic selection criteria

20. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting20 Scope of ERD Chapter Criteria for Including Technology Entries Devices and Architectures –  Published by 2 or more groups in archival literature and peer reviewed conferences, or  Published extensively by 1 group in archival literature and peer reviewed conferences  Technology Entry (by itself or integrated with CMOS) must address a major electronics market. Materials and Fabrication Technologies –  Materials and processes that address the specific material needs defined by emerging research device technology entries  Supporting disciplines – specify for crosscut TWGs  Metrologies  Modeling & simulation

21. Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting21 State Variable Device Data Representation Architecture Material CNT FETs Molecular SpintronicsQuantum Scaled CMOS Ferromagnetic Quantum Analog Digital Reconfigurable Cellular arrays Boolean Silicon Carbon NTs Macro molecules Complex metal oxides Quantum qubit Spin orientation Molecular state Electric charge Bio inspiredPhase state Linear Nanowires Conventional Scaled CMOS New Information Process Technologies A Taxonomy for Nano Information Processing Technologies

22. Work in Progress --- Not for Publication 22 ERD WG 3/20/09 Brussels IRC FxF Meeting ERD ITWG Emerging Research Devices Working Group Proposal for Assessing Technology Options for Emerging Research Memory Devices Jim Hutchby & Mike Garner Friday March 20, 2009

23. Work in Progress --- Not for Publication 23 ERD WG 3/20/09 Brussels IRC FxF Meeting Objective of IRC/ERD/ERM discussion of this request from Samsung, Hynix, and Micron ERD/ERM is seeking IRC guidance on whether we should conduct a review and assessment of emerging research memory technologies with the goal of recommending those most promising for detailed roadmapping and accelerated research. ♦Assess technology capability of being scaled beyond the 15nm node. ♦Identify precompetitive research required for top candidates to scale beyond the 15nm node ♦Process will be completed in April 2010 with an oral report to the IRC in the Spring ITRS Meeting followed by a written report/recommendation to the IRC.

24. Work in Progress --- Not for Publication 24 ERD WG 3/20/09 Brussels IRC FxF Meeting Assessment of Promising Emerging Memory Devices Samsung, Hynix, and Micron proposed that the ERD/ERM identify memory technologies needing more focused support Proposal: ERD & ERM hold a workshop in April 2010 to review and assess emerging research memory devices –Goal: Identify emerging research memory technologies that merit more detailed roadmapping and more focused research. –Process: Same Process as the Logic Assessment in 2008 Champions present Pros, Cons and research needed for technology Friendly critic presents balanced assessment White paper prepared on each memory and circulated prior to the meeting Face to Face Presentations & Discussion Voting on Promising Technology Identify Critical Research Needed

25. Work in Progress --- Not for Publication 25 ERD WG 2/26/2009 Straw Candidate Emerging Research Memory Technologies  Capacitive Memory  FeFET Memory  Resistive Memory  Nanoelectromechanical  STT MRAM  Thermal PCM  FUSE/Anti-FUSE  Nanowire PCM  Electrochemical Memory  Cation migration  Anion migration  Electronic Effects Memory  Charge trapping  Mott Transition  FE barrier effects  Macromolecular Memory  Molecular Memory

26. Work in Progress --- Not for Publication 26 ERD WG 2/26/2009 DRAFT GOAL With the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and assessment of specific emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and acceleration of pre-competitive*research and development. (*Pre-competitive refers to those technologies capable of being scaled beyond the 15nm node.)

27. Work in Progress --- Not for Publication 27 ERD WG 2/26/2009 DRAFT SCOPE The scope of the review of emerging research memory technologies will assess scalability beyond the 15nm node. –Identify precompetitive research needed to enable scaling beyond the 15nm node. –Assessment will encompass both stand-alone and, where different, embedded emerging research memory technologies.

28. Work in Progress --- Not for Publication 28 ERD WG 2/26/2009 Draft Timetable 1. Develop/decide process, milestones, timelineJuly 12, 2009 2.Develop invitation to advocates/proponents & friendly critics  Introduction  Potential of technology – fundamental limits  Barriers – Fundamental vs. technological/engineering  Evaluation Criteria  Definition of specific emerging research memory devices for roadmapping  Readiness in 10 - 15 years July 31 3.Identify  Major emerging research memory device candidates  Strong technical proponent and friendly critic teams and their leaders  Knowledgeable ERD/ERM mentor for each proponent team  Key questions to be addressed by the teams  Background materials for each technical candidate July 31 4.Issue invitations to team leaders, friendly critics, and ERD/ERM mentors and obtain their commitments Sept. 15 5.Obtain a white per & background materials from each candidate technology proponent team for ERD/ERM WG review Jan. 15, 2010 6.ERD/ERM WG review candidate emerging research memory devices candidates based on white papers & identify key questions using a formal process prior to Spring Europe FxF meeting. Mar. 15, 2010 7.Conduct a FxF review of categories with each proponent & friendly critic making a presentation April yy, 2010 Spring FXF Mtg. 8.On second day of ERD FxF meeting, discuss/decide ERD/ERM WG’s prioritized recommendation of narrowed emerging research memory devices options. This will include selection of specific devices for roadmapping within the recommended option April yy+1,2010 Spring FXF Mtg. 9.Write & submit report on ERD/ERM WG’s recommendationsMay 31, 2010

29. Work in Progress --- Not for Publication 29 ERD WG 3/20/09 Brussels IRC FxF Meeting Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Develop/decide process, milestones, timeline  Develop invitation to advocates & opponents  Introduction  Potential of technology – fundamental limits  Barriers – Fundamental vs. technological/engineering  Evaluation Criteria / Benchmark memory technology  Definition of maturing, high potential specific devices for roadmapping  Readiness in ~ 5 - 10 years

30. Work in Progress --- Not for Publication 30 ERD WG 3/20/09 Brussels IRC FxF Meeting Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Identify  Major emerging research memory technology candidates  Strong technical proponent and opponent teams and their leaders  Knowledgeable ERD/ERM mentor for each proponent team  Key questions to be addressed by the teams  Background materials for each technical candidate  Issue invitations to team leaders and obtain their commitments  Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review

31. Work in Progress --- Not for Publication 31 ERD WG 2/26/2009 REDO THIS SLIDE

32. Work in Progress --- Not for Publication 32 ERD WG 2/26/2009

33. Work in Progress --- Not for Publication 33 ERD WG 2/26/2009 Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Conduct a FxF review of categories with each proponent & friendly critic team making a presentation  On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Mentors will lead the discussion of their candidate technology  Write & submit report to the IRC on ERD/ERM WG’s recommendations

34. Work in Progress --- Not for Publication 34 ERD WG 2/26/2009 Decision Making & Majority Voting Scheme  Each member of ERD WG will be given a maximum of X votes to use in voting for their top X choices among the candidate technologies (Majority Voting scheme)  ERD/ERM WG members present in the FIRST DAY Workshop & the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation,  Only 0 or 1 vote can be cast for any candidate technology  Member does not have to use all X votes, but cannot use more than X votes.  All members can participate in the straw vote.  The Candidate Technologies will be ordered according to which received the largest number of votes.  Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus. REDO THIS SLIDE

35. Work in Progress --- Not for Publication 35 ERD WG 2/26/2009 ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY 9:20Review Process for selecting beyond CMOS emerging technologies 9:45Discuss Technologies 9:45NEMS Switch Technology 10:05Spin Torque Transfer Technology 10:25Carbon-based Nanoelectronics 10:45Break 11:00Atomic Switch / Electrochemical Metal Switch 11:20Collective Spin Devices (including M-QCA) 11:40Single Electron Transistors 12:00CMOL and FPNI REDO THIS SLIDE

36. Work in Progress --- Not for Publication 36 ERD WG 2/26/2009 ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d) 12:50Preliminary vote on technologies – Majority voting process 1:00Discuss preliminary results 1:45Second vote on technologies 2:00Discuss the leading technologies resulting from vote 2:30Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technologies REDO THIS SLIDE

37. Work in Progress --- Not for Publication 37 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Decision Making & Majority Voting Scheme  Each member of ERD WG will be given a maximum of 3 votes to use in voting for their top 3 choices among the candidate technologies (Majority Voting scheme)  ERD/ERM WG members present in the July 11 Workshop & the July 12 FxF meeting will be eligible to vote at July 12 meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation,  Only 0 or 1 vote can be cast for any candidate technology  Member does not have to use all 3 votes, but cannot use more than 3 votes.  All members can participate in the straw vote.  The Candidate Technologies will be ordered according to which received the largest number of votes.  Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.