1. Out-of-Order OpenRISC Stage 1: Implementation of OpenRISC on XUP5 board Project Characterization By: Vova Menis-Lurie Sonia Gershkovich Advisor: Mony Orbach Spring Semester 2012

2. Content: 1.Project Overview a. Goals b. Background and the challenge 2. Specifications a. OpenRISC 1200 b. Working Environment 3. Workflow 4. Timetable – Gantt Chart

3. Project Overview Project Goals Primary Goal: Implementation of Out-of-Order execution engine on the base of OpenRISC CPU Primary Goal – semester A: Creating a complete system-on-a-chip based OpenRISC, on XUP5 board, as a platform for further work, including: Choosing Configuration for the CPU Simulation and Synthesis Implementation Debugging Testing the system

4. Project Overview Our Goals Understanding of the fundamentals of computer architecture Acquiring computer designer’s skills, including experience in CPU design, computer organization, hardware implementation and debugging. Learning and practicing Verilog HDL (OpenRISC implementation language)

5. Project Overview Background OpenRISC is an OpenCores community project aiming to develop a series of general purpose Open Source RISC architectures Only one architecture has been released till now – OpenRISC 1000 Configurable implementation, written in Verilog HDL has been introduced - OpenRISC 1200, supporting Basic Instruction Set, DSP extension and FP extension. Our challenge is to configure the convenient architecture implementation for XUP5 board, and create the environment to ensure proper work and testability of the system.

6. The OpenRISC 1200 Starting Configuration for Project (may be changed) Original Unit Scheme

7. The OpenRISC 1200 IMMUPICDC CPU IC DWBIWB DUPMTT

8. I/O Signals Data Wishbone Signals Instruction Wishbone Signals System Signals Optional Units Signals

9. Working Environment – Hardware XUP5 Board

10. OR1200 on XUP5

11. Working Environment - Software Project Management - ISE (optional – PlanAhead for special tasks) Simulation - ISim(ISE); - or1ksim (optional, requires Unix OS) -Icarus (optional) Synthesis - XST(ISE) Debugging: - ChipScope - or1ksim (optional, requires Unix OS)

12. Workflow: 1.Choosing the configuration: what optional/configurable parts we will include (interrupts/cache/debug unit, etc.). 2. Complete system compilation, including CPU and buses and other parts according to section 1. 3. Synthesis and post-synthesis simulation, pin-assignments. 4.Burning the system to the chip and basic debugging. 5.Choosing a way to test the system, for example creating simple C program and executable file to be run on the OR1200. 6.After verifying the design, go ahead to creating and implementation OoO unit (semester B). Hello world!

13. Project Timetable- Gantt Chart

14. Thank you!