1. Intro MIPS Computer Organization I 1 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens The Stored Program Computer 1945: John von Neumann – Wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC – also Alan Turing… Konrad Zuse… Eckert & Mauchly… The basic structure proposed in the draft became known as the “von Neumann machine” (or model). – a memory, containing instructions and data – a processing unit, for performing arithmetic and logical operations – a control unit, for interpreting instructions

2. Intro MIPS Computer Organization I 2 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens von Neumann Model Abstraction of von Neumann implements a next state function stores both program instructions and data

3. Intro MIPS Computer Organization I 3 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Memory 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 10100010 2 k x m array of stored bits Address – unique (k-bit) identifier of location Contents – m-bit value stored in location Basic Operations LOAD – read a value from a memory location STORE – write a value to a memory location

4. Intro MIPS Computer Organization I 4 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Interface to Memory How does processing unit get data to/from memory? MAR: Memory Address Register MDR: Memory Data Register To LOAD a location (A): – Write the address (A) into the MAR. – Send a “read” signal to the memory. – Read the data from MDR. To STORE a value (X) to a location (A): – Write the data (X) to the MDR. – Write the address (A) into the MAR. – Send a “write” signal to the memory.

5. Intro MIPS Computer Organization I 5 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Hardware Level Organization PCMAR IRMBR I/O AR I/O BR Ex Unit CPU I/O Module buffers Main Memory Instruction Data 0 n-1 System Bus PC= program counter IR= instruction register MAR= memory address register MBR= memory buffer register I/O AR= I/O address register I/O BR= I/O buffer register Major components: -memory -central processing unit -registers -the fetch/execute cycle (the hardware process)

6. Intro MIPS Computer Organization I 6 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Central Processing Unit Control -decodes instructions and manages CPU’s internal resources Registers -general-purpose registers available to user processes -special-purpose registers directly managed in fetch/execute cycle -other registers may be reserved for use of operating system -very fast and expensive (relative to memory) -hold all operands and results of arithmetic instructions (on RISC systems) -save bits in instruction representation Data path or arithmetic/logic unit (ALU) -operates on data

7. Intro MIPS Computer Organization I 7 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens memory for data, programs, compilers, editors, etc. Stored Program Concept Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the “next” instruction and continue Instructions are collections of bits Programs are stored in memory, to be read or written just like data PCMAR IRMBR I/O AR I/O BR Ex Unit CPU Main Memory Instruction Data 0 n-1

8. Intro MIPS Computer Organization I 8 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Of course, on most systems several programs will be stored in memory at any given time. On most contemporary systems instructions of only one of those will be executed at any given instant. Stored Program Concept The operating system will rapidly switch among the eligible processes, producing the illusion that several programs are executing at the same time. PCMAR IRMBR I/O AR I/O BR Ex Unit CPUMain Memory PowerPoint pgm (machine code) vim (machine code) GIS source code (data) g++ (machine code)

9. Intro MIPS Computer Organization I 9 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Fetch/Execute Cycle Sometimes called the hardware process… executes continuously. Steps: -fetch an instruction from memory to the instruction register -increment the program counter register (by the instruction length) -decode the instruction (in the control unit) -fetch operands, if any, usually from registers -perform the operation (in the data path); this may modify the PC register -store the results, usually to registers Fetch StageExecute Stage Fetch Next Instruction Execute Instruction START HALT

10. Intro MIPS Computer Organization I 10 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Simplified MIPS Datapath Register File Memory ALU

11. Intro MIPS Computer Organization I 11 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Finite State Machine So, where's the FSM? Input Next Instruction Execute Instruction Current State Contents of registers and memory Output devices Input devices

12. Intro MIPS Computer Organization I 12 CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens Control Unit State Diagram Here's a state machine diagram for the MIPS control logic we'll be studying: