1. Fall 2004EE 3563 Digital Systems Design EE3563 Chapter 7, 8, 10 Reading Assignments  7.1, 7.2, 7.3  8.1, 8.2.1-8.2.3, 8.2.5  8.4.1-8.4.3  8.5.1, 8.5.2, 8.5.4  8.8  10.1, 10.2, 10.3.1-10.3.4, 10.4.1, 10.4.2

2. Fall 2004EE 3563 Digital Systems Design EE3563 Revisit Transfer Curve

3. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  A state machine has several components: –Next-State Logic Combinational logic that determines what the next state should be –State Memory Value of output of flip flops –Output Logic Flip flop output is not necessarily the final output For example, output might be the ANDing of the flip-flop output  Clocked means that transitions only happen on the tick of a clock  Synchronous means that all transitions happen at the same time – the tick of the clock  There are 2 n distinct states with n being the number of binary state variables

4. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Mealy machine – output logic takes as input the current state as well as the machine inputs

5. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Moore machine – output logic is solely based upon the current state  If some outputs depend on inputs and some don’t, then it is classified as a Mealy machine

6. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Outputs may be pipelined as well, that is, the final outputs depend upon the state and inputs of the previous clock period  Pipelining can be very efficient, much like an assembly line  When a machine has multiple stages, pipelining can allow each stage to work in parallel thereby increasing efficiency

7. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  The functional behavior of a latch or flip-flop can be described with a characteristic equation  It specifies the next state as a function of inputs and current state

8. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  State machine with two positive-edge-triggered D flip-flops

9. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Transition Table, State Table, State/Output Table

10. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  State Diagram for D-FF Mealy State Machine

11. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  State Diagram for D-FF Moore State Machine

12. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  D-FF State Machine Redrawn

13. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Steps for analyzing a clocked synchronous circuit: –Get excitation equations –Substitute excitation equations into flip-flop characteristic equations –Use transition equations to construct transition table –Get output equations –Create transition/output table –Name states and substitute state names for state-variable combinations to create state output table –Draw a state diagram corresponding to the state/output table  The text goes through these steps for a different example on pages 559-560  We will go through the steps, but using the J-K flip-flop example

14. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Get Excitation Equations

15. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Get Excitation Equations

16. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Substitute excitation equations into flip-flop characteristic equations to get transition equations Characteristic EquationsExcitation Equations Transition Equations

17. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Use transition equations to construct transition table

18. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Get output equation

19. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Get output equation  Z = X * Q0*Q1 + Y*Q0’*Q1’

20. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Create transition/output table Transition Output Table

21. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Name states and substitute state names for state-variable combinations to create state output table State Output Table

22. Fall 2004EE 3563 Digital Systems Design EE 3563 Clocked Synchronous State Machines  Draw a state diagram corresponding to the state/output table