1. Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits Jun Seomun, Jaehyun Kim, Youngsoo Shin Dept. of Electrical Engineering, KAIST, KOREA

2. Leakage Power in Technology Scaling 250 200 150 100 50 0 Power (W) Technology 0.25µ 0.18µ 0.13µ 0.10µ 0.07µ Dynamic Power Leakage Power Intel Corporation, 2002

3. Overview of Mixed V t Technique Mixed V t CMOS Mixed V t CMOS –Low V t : fast but high leakage –High V t : low leakage but slow Value of mixed V t is limited Value of mixed V t is limited –It considers only the combinational portion of circuits Low V t High V t High V t gates can be assigned some non–critical path Critical path Initially all low V t

4. Motivation Leakage of sequential elements Leakage of sequential elements –Sequential elements take large proportion in many controllers s298s344s349 s382 s400s444 s526s641s713s838 s9234 Flip-flop Comb. 100% 80% 60% 40% 20% 0% s298s344s349 s382 s400s444s526s641 s713s838 s9234 Mixed V t

5. Why Not High V t Flip-Flop? Large effects on the slack Large effects on the slack –The delay overhead of high V t flip-flops is larger than that of the other high V t combinational gates –Flip-flop typically affects more than one of the timing paths in a circuit 0 5 10 15 20 25 F/FINVNAND2NOR2NAND3NAND4 0 1 2 3 4 s298s344s349s400s444s526s641s713s838 s9234 [Average # fanout timing paths on F/Fs] / [Average # fanout timing paths on comb. Gates] Delay of high V t gate - delay of low V t gate

6. Mixed L gate flip-flop Mixed L gate flip-flop –Lager L gate transistor Smaller delay overhead than high V t transistor Smaller delay overhead than high V t transistor Footprint of gate remains almost the same Footprint of gate remains almost the same –Selective assignment of larger L gate in flip-flop Smaller delay overhead than entire assignment in flip-flop Smaller delay overhead than entire assignment in flip-flop Maximum reduction can be obtained up to same amount of leakage reduction with the case when all gates are larger L gate Maximum reduction can be obtained up to same amount of leakage reduction with the case when all gates are larger L gate Unequal leakage along with values of D and Q Unequal leakage along with values of D and Q –Four kinds of SFFs Characterized to minimize leakage corresponding to four states (D & Q) Characterized to minimize leakage corresponding to four states (D & Q) SF 00, SF 01, SF 10 and SF 11 SF 00, SF 01, SF 10 and SF 11 Skewed Flip-Flops

7. Design of an SFF (in case of SF 00 ) Design of an SFF (in case of SF 00 ) –Assume CK = 0 in idle state (clock gating) clk1clkclk clk clk clk clk clk clk 0 1 0 110 1 0 1 0 0QDCK clk 00001 Larger L gate

8. Skewed Flip-Flops Skewed flip-flops Skewed flip-flops clk Q D CK clk SF 00 SF 01 SF 10 SF 11

9. Leakage Characteristic of SFFs 45-nm PTM, 4 nm biasing 45-nm PTM, 4 nm biasing 0 400 800 1200 0/00/11/01/1 (a) SF 00 D/Q 0 400 800 1200 0/00/11/01/1 (b) SF 01 D/Q 0 400 800 1200 0/00/11/01/1 (c) SF 10 D/Q 0 400 800 1200 0/00/11/01/1 (d) SF 11 D/Q Current [nA] Orig.SF 00Orig.SF 01 Orig.SF 10Orig.SF 11

10. 45-nm PTM, 4 nm biasing 45-nm PTM, 4 nm biasing Timing Characteristic of SFFs 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 0 10 20 30 Rising T su Falling Rising T c-q Falling (a) SF 00 Rising T su Falling Rising T c-q Falling (b) SF 01 Rising T su Falling Rising T c-q Falling (c) SF 10 Rising T su Falling Rising T c-q Falling (d) SF 11 Delay [ps] Orig.SF 00 Orig.SF 01 Orig.SF 10 Orig.SF 11 (a) Rising T su (b) Falling T su T su ' T su T su ' T 1 T 1 ' T 1 ' T 1 D clk T su D clk CK (rising edge) 0.9 0 0.9 0 Orig. SF 00 Orig. SF 00 TimeTime Voltage [V]

11. SFF Transformation Utilize SFFs while maintaining timing constraints – –Input : netlist & idle state probabilities of flip-flops – –Output : new netlist with skewed flip-flops Skewed flip-flop transformation under timing constraints Initial SFF assignment Flip-flop transformation Find critical path Find candidate Substitute Netlist & Idle state probabilities Mixed V t assignment on combinational subcircuits

12. For a smoother transition For a smoother transition –HSF 0 : unchanged setup time delay –HSF 1 : unchanged clock-to-q delay Half Skewed Flip-Flops (HSFs) HSF 0 HSF 1

13. SFF Transformation Algorithm Select a flip-flop to be transformed Select a flip-flop to be transformed –Find critical path –Find candidate Both ends of the most critical path Both ends of the most critical path Larger timing improvement Larger timing improvement Substitute Substitute –(1) Most effective SFFs in terms of delay given position and phase of transition –(2) If (1) fails, try HSFs –(3) If (2) fails, use the original flip-flops

14. Experimental Results For ISCAS benchmark circuits (45-nm PTM library) For ISCAS benchmark circuits (45-nm PTM library) Benchmark Mixed V t only SFX + Mixed V t Name # Gates # FFs Comb. (uA) SE (uA) Total (uA) Comb. (x) SE (x) Total (x) s298130143013430.970.440.81 s344144153115460.990.540.86 s349142153115461.000.540.86 s382185213819571.060.380.84 s400198213819571.120.360.87 s444199214919681.120.360.91 s526258214119600.990.550.85 s641206193018480.990.450.79 s713206193418521.000.450.81 s8384163270301001.030.370.83 s537815341632441553991.070.420.82 s923414571352801214011.030.360.83 Avg.1.040.440.84

15. Comparison of Mixed V t Flip-Flop s298s344s349s400s444s526s641s713s838 s9234 s382 Mixed V t FFs + Mixed V t comb. SFX + Mixed V t comb. 0.6 0.7 0.8 0.9 1.0 0 1 2 3 4 s298s344s349s400s444s526s641s713s838 s9234 [Average # fanout timing paths of F/Fs] / [Average # fanout timing paths of comb. Gates]

16. Conclusion Proposed Skewed Flip-Flops Proposed Skewed Flip-Flops –The set of mixed L gate flip-flops –Skewed characteristics in terms of leakage and delay A heuristic algorithm that substitutes SFFs A heuristic algorithm that substitutes SFFs –An average leakage saving of 16% is achieved, compared to the use of mixed V t alone