1. Nano-Array Hybrid CMOS/Nanoelectronic Circuits e. g. CMOS, FPNI

2. CMOL, FPNI, Nano-Array Realism –We were charged to find a magic solution that would continue scaling in power and speed, given that density scaling looks healthy –CMOL and FPNI continue scaling in density but are not a magic solution for power and speed –Could provide for progress while reinforcing realistic expectations Risk Reduction/Infrastructure/Horizontal Solution –Circuit works with 4 devices presented at this meeting, and others too

3. Technical Advantages Enables features smaller than lithographic resolution from a manufacturing process that is not as technically challenging as lithography –Drawing parallel lines or nano-imprint Stacks on top of CMOS thus enabling additional function without taking away real estate for CMOS (2½-D) Can be used to create diverse structures –(non-volatile) memory –Logic (FPGA-like)

4. Possible Advantage over CMOS CMOS, FPNI will not beat the fundamental limits on CMOS logic However, CMOS performance includes a major effect due to wire CMOL, FPNI alter the CMOS performance equation at the wire level and could offer a modest boost “Beyond CMOS” –Addressed by Andre’s analysis that benefit was partly due to lots of devices and partly due to reduced linewidth

5. Roadmap Advocates prepared a roadmap –We can debate the realism of the the advocates’ roadmaps, but the mere presence of a roadmap is a sign of considerable maturity Speed, power and density offer some advantage over plain CMOS

6. Design Tools already exist for design with CMOL, FPNI, etc. –We can debate the maturity of the tools, but the mere presence of tools is a sign of considerable maturity

7. Logic Family FIT rates estimated Defect tolerance included Power estimates, including wire delay

8. Possible Secondary Benefits Andre showed head-to- head competition with CMOS/ASIC – looked like a good competition. What might come beyond competing with CMOS? Advantages that could come from crosspoint device –non-volitile memory, which would introduce new function –RAD/SEU hard, which would be an advance “Design modality choice” – designer could optimize across design by ASIC, nano-array, or a mixture or design styles