1. 1 Performance Guarantees for Internet Routers ISL Affiliates Meeting April 4 th 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University nickm@stanford.edu www.stanford.edu/~nickm

2. 2 What a Router Looks Like Cisco GSR 12416Juniper M160 6ft 19” 2ft Capacity: 160Gb/s Power: 4.2kW 3ft 2.5ft 19” Capacity: 80Gb/s Power: 2.6kW

3. 3 Basic Architectural Components of an IP Router Control Plane Datapath per-packet processing Switching Forwarding Table Routing Table Routing Protocols

4. 4 Generic Router Architecture Lookup IP Address Update Header Header Processing DataHdrDataHdr ~1M prefixes Off-chip DRAM Address Table Address Table IP AddressNext Hop Queue Packet Buffer Memory Buffer Memory ~1M packets Off-chip DRAM

5. 5 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory

6. 6 High Performance Networking Research Group 1.Adisak Mekkitikul: Crossbar scheduling algorithms that provide 100% throughput. 2.Pankaj Gupta: IP address lookup and classification algorithms. 3.Sundar Iyer: Parallel packet switches; High performance packet buffers; Distributed shared memory routers. 4.Isaac Keslassy, Shang-tse Chuang: Incorporating optics into routers. 5.Pablo Molinero Fernandez: The use of circuit switching in the Internet. 6.Nandita Dukkipati, Rui Zhang: Congestion control for short- lived flows. 7.Yashar Ganjali: Multipath routing. Graduated

7. 7 Performance metrics of routers 1. Capacity  “maximize C, s.t. volume < 2m 3 and power < 5kW” 2. Throughput  Operators like to maximize usage of expensive long-haul links.  This would be trivial with work-conserving output- queued routers 3. Controllable Delay  Some users would like predictable delay.  This is feasible with output-queueing plus weighted fair queueing (WFQ). WFQ

8. 8 The Problem  Output queued switches are impractical R R R R DRAM NR data

9. 9 Memory Bandwidth Commercial DRAM 1. It’s hard to keep up with Moore’s Law:  The bottleneck is memory speed.  Memory speed is not keeping up with Moore’s Law. DRAM 1.1x / 18months Moore’s Law 2x / 18 months Router Capacity 2.2x / 18months Line Capacity 2x / 7 months

10. 10 Potted history 1. [Karol et al. 1987] Throughput limited to by head- of-line blocking for Bernoulli IID uniform traffic. 2. [Tamir 1989] Observed that with “Virtual Output Queues” (VOQs) Head-of-Line blocking is reduced and throughput goes up.

11. 11 Potted history 3. [Anderson et al. 1993] Observed analogy to maximum size matching in a bipartite graph. 4. [M et al. 1995] (a) Maximum size match can not guarantee 100% throughput. (b) But maximum weight match can – O(N 3 ). 5. [Mekkittikul and M 1998] A carefully picked maximum size match can give 100% throughput. Matching O(N 2.5 )

12. 12 Potted history Speedup 5. [Chuang, Goel et al. 1997] Precise emulation of an output queued switch is possible with a speedup of two and a “stable marriage” scheduling algorithm. 6. [Prabhakar and Dai 2000] 100% throughput possible for maximal matching with a speedup of two.

13. 13 Potted history Newer approaches 7. [Tassiulas 1998] 100% throughput possible for simple randomized algorithm with memory. 8. [Giaccone et al. 2001] “Apsara” algorithms. 9. [Iyer and M 2000] Parallel switches can achieve 100% throughput and emulate an output queued switch. 10. [Chang et al. 2000] A 2-stage switch with a TDM scheduler can give 100% throughput. 11. [Iyer, Zhang and M 2002] Distributed shared memory switches can emulate an output queued switch.

14. 14 Basic Switch Model A 1 (n) S(n) N N L NN (n) A 1N (n) A 11 (n) L 11 (n) 11 A N (n) A NN (n) A N1 (n) D 1 (n) D N (n)

15. 15 Some definitions 3. Queue occupancies: Occupancy L 11 (n) L NN (n)

16. 16 Some definitions of throughput When traffic is admissible

17. 17 Scheduling algorithms to achieve 100% throughput 1. When traffic is uniform (Many algorithms…) 2. When traffic is non-uniform, but traffic matrix is known Technique: Birkhoff-von Neumann decomposition. [Chang ‘99] 3. When matrix is not known. Technique: Lyapunov function. [M et al. ‘96] 4. When algorithm is pipelined, or information is incomplete. Technique: Lyapunov function. [Keslassy & M ’01] 5. When algorithm does not complete. Technique: Randomized algorithm. [Tassiulas ’00] 6. When there is speedup. Technique: Fluid model. [Dai & Prabhakar ’00] 7. When there is no algorithm. Technique: 2-stage load-balancing switch. [Chang ’01] Technique: Parallel Packet Switch. [Iyer & M ’01]

18. 18 When the traffic matrix is not known

19. 19 Throughput results Theory: Practice: Input Queueing (IQ) Input Queueing (IQ) Input Queueing (IQ) Input Queueing (IQ) 58% [Karol, 1987] IQ + VOQ, Maximum weight matching IQ + VOQ, Maximum weight matching IQ + VOQ, Sub-maximal size matching e.g. PIM, iSLIP. IQ + VOQ, Sub-maximal size matching e.g. PIM, iSLIP. 100% [M et al., 1996] Different weight functions, incomplete information, pipelining. Different weight functions, incomplete information, pipelining. Randomized algorithms 100% [Tassiulas, 1998] 100% [Various] Various heuristics, distributed algorithms, and amounts of speedup Various heuristics, distributed algorithms, and amounts of speedup IQ + VOQ, Maximal size matching, Speedup of two. IQ + VOQ, Maximal size matching, Speedup of two. 100% [Dai & Prabhakar, 2000]