1. Pipeline Hazards

2. CS5513 Fall 20062 Pipeline Hazards Situations that prevent the next instructions in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. –Structural Hazards –Data Hazards –Control Hazards Hazards can make it necessary to stall the pipeline.

3. CS5513 Fall 20063 Pipeline Hazards When an instruction is stalled, all instructions issued later than the stalled instruction are also stalled. No new instructions are fetched during the stall.

4. CS5513 Fall 20064 Structural Hazards Hardware cannot support the combination of instructions that we want to execute in the same clock cycle. –Suppose we have a single memory instead of two memories.

5. CS5513 Fall 20065 Control Hazards This arises from the need to make a decision based on the results of one instruction while others are executing. –branch instruction –Pipeline stall (or bubble) How can we overcome this problem?

6. CS5513 Fall 20066 Branch Hazards To minimize the branch penalty, put in enough hardware so that we can test registers, calculate the branch target address, and update the PC during the second stage.

7. CS5513 Fall 20067 Data Hazards An instruction depends on the results of a previous instruction still in the pipeline. e.g. add $s0, $t0, $t1 sub $t2, $s0, $t3 The add instruction doesn’t write the result until the 5 th stage. => 3 bubbles

8. CS5513 Fall 20068 Solution forwarding (or bypassing): getting the missing item early from the internal resources. e.g. as soon as the ALU creates the sum for the add, we can supply it as the input for the subtract.