1. Chapter 1 Performance & Technology Trends Read Sections 1.5, 1.6, and 1.8

2. CPE 432 Chapter 1.2 Chapter 1 — Computer Abstractions and Technology — 2 Section 1.5: The Power Wall

3. CPE 432 Chapter 1.3 Chapter 1 — Computer Abstractions and Technology — 3 Power Trends In CMOS IC technology ×1000 ×30 5V → 1V  Clock rates hit a “power wall”

4. CPE 432 Chapter 1.4 Chapter 1 — Computer Abstractions and Technology — 4 The power wall Performance was always improved by increasing frequency (up to 2004) However by 2006, companies could not reduce generated power and remove more heat Hence performance improvement could not be achieved by increasing frequency because of the increased power generated >>>>> THE POWER WALL How else can we improve performance?

5. CPE 432 Chapter 1.5 Chapter 1 — Computer Abstractions and Technology — 5 Read Section 1.6: The Sea Change The Switch to Multiprocessors

6. CPE 432 Chapter 1.6 Chapter 1 — Computer Abstractions and Technology — 6 Uniprocessor Performance Uniprocessor performance is constrained by power, instruction- level parallelism, memory latency

7. CPE 432 Chapter 1.7Dr. W. Abu-Sufah A Sea Change is at Hand  The power challenge has forced a change in the design of microprocessors l Since 2002 the rate of improvement in the response time of programs on desktop computers has slowed from a factor of 1.5 per year to less than a factor of 1.2 per year  As of 2006 all desktop and server companies are shipping microprocessors with multiple processors – cores – per chip ProductAMD Barcelona Intel Nehalem IBM Power 6Sun Niagara 2 Cores per chip4428 Clock rate2.5 GHz~2.5 GHz?4.7 GHz1.4 GHz Power120 W~100 W? 94 W  Plan is to double the number of cores per chip per generation (about every two years) Plan not followed!!

8. CPE 432 Chapter 1.8Dr. W. Abu-Sufah Multicore microprocessors  Require explicitly parallel programming l In single core microprocessors, hardware implemented instruction level parallelism to execute multiple instructions IN PARALLEL l Instruction level parallelism is hidden from the programmer l Parallel programming is hard (harder) to do. Involves: -Programming for performance -Load balancing -Optimizing communication and synchronization 8 With the introduction of multicore microprocessors, The Free Lunch Era Ended !!!

9. CPE 432 Chapter 1.9Dr. W. Abu-Sufah Read Section 1.8: Pitfalls and Fallacies

10. CPE 432 Chapter 1.10Dr. W. Abu-Sufah Pitfalls and Fallacies  Pitfalls: Easily made mistakes  Fallacies: l Errors l Myths l…l…

11. CPE 432 Chapter 1.11Dr. W. Abu-Sufah Pitfall: Amdahl’s Law  Pitfall: Improving an aspect of a computer and expecting a proportional improvement in overall performance Can’t be done! Example: multiply operations account for 80 seconds of a 100 seconds run time of a program How much improvement in multiply performance to get the program to run 5 times faster (i.e. in {100/5} = 20s)?

12. CPE 432 Chapter 1.12Dr. W. Abu-Sufah Amdahl’s Law Best Speedup overall you could ever hope to do: ExTime old ExTime new fraction enhanced

13. CPE 432 Chapter 1.13 Amdahl’s Law example 13 New CPU 10X faster I/O bound server, so 60% time waiting for I/O Apparently, its human nature is to be attracted by 10X faster, vs. keeping in perspective that it is just 1.56X faster

14. CPE 432 Chapter 1.14 Amdahl’s Law example: Make the common case fast 14 Fraction = 0.1, Speedup = 10 Fraction = 0.9, Speedup = 10

15. CPE 432 Chapter 1.15 15 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn’t account for Differences in ISAs between computers Differences in complexity between instructions

16. CPE 432 Chapter 1.16Dr. W. Abu-Sufah Pitfall: MIPS as a Performance Metric (cont.)  How should MIPS be computed? l It is not the maximum theoretical MIPS quoted by the manufacturer. CPI varies between programs on a given CPU