1. 241-208 CH51 Chapter 5 Combinational Logic By Taweesak Reungpeerakul

2. 241-208 CH52 Contents Basic Combinational Logic Circuits Implement SOP and POS using Basic Logic Gates Universal Property of NAND and NOR Combinational Logic using NAND and NOR Operation with Pulse Waveforms Digital System Application

3. 241-208 CH53 5.1 Basic Combinational Logic Circuit Inputs A B C AB AC BC OUT 00 0 00 0 0 0 0 1 00 0 0 0 1 0 00 0 0 0 1 1 00 1 1 1 0 0 00 0 0 1 0 1 01 0 1 1 1 0 10 0 1 1 1 1 11 1 1 BC AB AC AB+AC+BC Actually AND-OR is a form of SOP expression ! Aims: Able to analyze&apply AND-OR,AND-OR-INV, XOR, XNOR circuits

4. 241-208 CH54 AND-OR-INV Logic Invert AND-OR in SOP  AND-OR-INV in POS Prove ?? AB+AC+BC =(A+B)(A+C)(B+C)

5. 241-208 CH55 XOR OUT = AB + AB

6. 241-208 CH56 XNOR OUT = AB + AB = AB + AB

7. 241-208 CH57 5.2 Implementing Combinational Logic Ex#1: OUT = ABC+DE Ex#2: OUT = A(BC+DE) Aims: Able to implement a logic circuit from a Boolean expression and truth table and also able to minimize logic circuit.

8. 241-208 CH58 From Truth Table Truth Table A B C OUT 0 0 00 0 0 11 0 1 01 0 1 10 1 0 00 1 0 11 1 1 00 1 1 10 If you should SOP form then just considering outputs “1s”

9. 241-208 CH59 Example Truth Table A B C OUT 0 0 01 0 0 11 0 1 00 0 1 10 1 0 00 1 0 11 1 1 00 1 1 11 Table  Logic Circuit  Karnaugh Map  Simplified Circuit Minimize, don’t forget to use K-Map !!

10. 241-208 CH510 5.3 Universal Property of NAND&NOR INV, OR, AND, and NOR created by using NAND gates INV NOR AND OR Aims: implement OMV, OR, AND, and NOR using NAND or vice versa

11. 241-208 CH511 Universal Property of NOR INV, OR, AND, and NAND created by using NOR gates INV NAND AND OR

12. 241-208 CH512 5.4 Combinational Logic using NAND & NOR NAND; OUT = AB+CD = AB+CD = (AB)(CD) Aims: implement logic function using NAND/NOR gates

13. 241-208 CH513 Dual Symbols of NAND, i.e. NAND+Negative-OR Always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble. ABC AB+C

14. 241-208 CH514 Example: implemented by NAND Ex1: ABC+DE Ex2: ABC+D+E

15. 241-208 CH515 Combinational Logic using NOR NOR; (A+B)(C+D) = (A+B)(C+D) = (A+B)+(C+D)

16. 241-208 CH516 Dual Symbols (A+B)+C (A+B)C

17. 241-208 CH517 5.5 Operation with Pulse Waveforms C D Logic circuit  Timing diagram Aims: analyze combination logic circuits with pulse waveform inputs. develop a timing diagram for any given combination logic circuit with specified inputs Determine the output waveform ?

18. 241-208 CH518 Develop logic circuit from waveforms Not in the form of NAND gates only yet ! Transform….. (use dual symbols)

19. 241-208 CH519 5.6 Digital System Application From switches MOTORS

20. 241-208 CH520 Truth Table S 1 S 2 S 3 S 4 M 1 M 2 M 3 M 4 00 0 00000 00 0 10001 00 1 00010 00 1 10000 01 0 00000 01 0 10000 01 1 00000 01 1 10000 10 0 01000 10 0 11001 10 1 01010 1 0 1 10000 11 0 01100 11 0 10000 11 1 01110 11 1 10000

21. 241-208 CH521 Develop logic circuit from Truth Table 1 11 1 1 For Motor M1 S1S4S1S4 S1S2S3S1S2S3