1. ES 244: Digital Logic Design Chapter 4 Chapter 4: Combinational Logic Uchechukwu Ofoegbu Temple University

2. ES 244: Digital Logic Design Chapter 4 One-bit Carry Ripple Adder – s = sum –c out – carry-out –a, b = added bits –C = carry in abcc out s 00000 00101 01001 01110 10001 10110 11010 11111 – –S = a’b’c+a’bc’+ab’c’+abc – –c out = a’bc+ab’c+abc’+abc – – = bc+ac+ab – –S = c(a’b’+ab)+c’(ab’+a’b) – –c out = c(a+b)+ab – –S = c(aΦb)’+c’(aΦb) = c Φ(aΦb) – –Xor can be replaced with 4 two input NAND gates – –c out = c(a+b)+ab 5 three-input NAND, 3 two-input NAND, 1 four- input NAND, and three not gates if complemented inputs are not available 12 two-input NAND, two not gates or 9 two-input NAND gates assuming all input are available both complemented and uncomplemented 9 two-input NAND gates assuming all input are available both complemented and uncomplemented 2 two-input XOR, 3 two-input NANDs, 1 three- input OR

3. ES 244: Digital Logic Design Chapter 4 One-bit Full Binary Adder Gate implementation for the One-bit Full Adder n-bit “ripple-carry” binary adder Worst case propagation delay – 2n time units; Gate delay=1

4. ES 244: Digital Logic Design Chapter 4 Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Gate Delay through a 1-bit Adder

5. ES 244: Digital Logic Design Chapter 4 Gate Delay through an n-bit Adder 1.Delay from inputs to c out + 2.(n-2)*delay from c in to c out + 3.Max(delay from c in to c out or c in to s) For the multilevel adder: 5∆ + 2(n-2) ∆ + 3 ∆ = (2n+4) ∆ What is the delay for a 64 bit adder? Total delay does not have to be so long!!

6. ES 244: Digital Logic Design Chapter 4 SOP minimization for two-bit adders Complex equations Fan-in limitations With a maximum fan-in of 7, adding n-bit would have a total delay of (n+1)∆ Four-bit adders 7483, 7483A, 74283 – differ only in pin connections Produces the sum with four-level inputs Uses combination of NAND, NOR, AND, NOT and XOR gates c in to c out = 3Delay from c in to c out = 3 ∆ Total delay = of (3/4 n+1)∆ 4-bit adders are cascaded for larger adders Gate Delay Improvements

7. ES 244: Digital Logic Design Chapter 4 One-bit Full Binary Adder Gate implementation for the One-bit Full Adder n-bit “ripple-carry” binary adder Worst case propagation delay – 2n time units; Gate delay=1 abc s C out

8. ES 244: Digital Logic Design Chapter 4 Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Gate Delay Improvements

9. ES 244: Digital Logic Design Chapter 4 Carry-Look-Ahead Adder Carry generate signal (g) is 1 if that stage of the adder has a carryout of 1 whether or not there was a carry-in Carry propagate signal (p) is 1 if that stage of the adder has a carryout of 1 if he carry-in is 1 Both g and p can be generated for all n bits in 1 gate delay. The carry out is 1 if the last bit generated a carry, or if it propagated a carry and the stage below it generated one. All the carries can be generated in 2 additional delays after g and p are available, independent of n. All sums can be generated in 4∆, independent of n. Gate Delay Improvements

10. ES 244: Digital Logic Design Chapter 4 One-bit Full Binary Subtractor/Adder Subtract y from x, with a borrow-in from the previous bit position, b in –d: difference – b out : borrow-out xyb in b out d 00000 00111 01011 01110 10001 10100 11000 11111

11. ES 244: Digital Logic Design Chapter 4 Organization of a 1-bit comparator Compares two numbers to determine if –A is less than B –A is equal to B –A if greater than B Can be extended to any bit size

12. ES 244: Digital Logic Design Chapter 4 Truth Table for Simple 1-bit Comparator A2A2 B2B2 A1A1 B1B1 Y: A=B Y: A>B Y A<B 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1.In groups, come up with a minimum SOP expression for this simple comparator. Assume all inputs are available in both complimented and uncomplemented versions, design a logic circuit for your algebraic expression What is the minimum delay for your design

13. ES 244: Digital Logic Design Chapter 4 Selects one of several outputs when activated n-bit binary number results in 2 n output lines Binary Decoders

14. ES 244: Digital Logic Design Chapter 4 Binary Decoders Selected output is high

15. ES 244: Digital Logic Design Chapter 4 Binary Decoders Selected output is low

16. ES 244: Digital Logic Design Chapter 4 Binary Decoders Selected output is high only when Enable bit is high or Enable Prime is low

17. ES 244: Digital Logic Design Chapter 4 Active Low and three enable bits Active when ALL THREE enable bits are active Binary Decoders

18. ES 244: Digital Logic Design Chapter 4 Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Binary Decoders

19. ES 244: Digital Logic Design Chapter 4 Exact Opposite of a binary decoder Used to select a device from several possible devices If only one of the inputs can be 1, then the truth table for a 4-2 encoder is: Binary Encoders A0A0A0A0 A1A1A1A1 A2A2A2A2 A3A3A3A3 z0z0z0z0 z1z1z1z1 100000 010001 001010 000111 Z 0 =A 2 +A 3 Z 1 =A 1 +A 3 What is the difference between Device A 0 and when there is no device signaling?

20. ES 244: Digital Logic Design Chapter 4 Priority Encoders

21. ES 244: Digital Logic Design Chapter 4Multiplexers A switch that is used to pass one input as a function of select inputs

22. ES 244: Digital Logic Design Chapter 4Multiplexers

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