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NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

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Presentation on theme: "NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning."— Presentation transcript:

1 NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

2 311_07 NAND and NOR Gates 2

3 DeMorgan's Laws  (X ∙ Y)' = X' + Y'  (X + Y)' = X' ∙ Y' 311_073

4 Functionally Complete Set  Any function can be realized using only NAND gates 311_074

5 SOP to NAND-NAND G = WXY + YZ 5

6 311_07 MOSFETs NMOS (n-channel) PMOS (p-channel) OFF ON OFF 6

7 CMOS Inverter 311_077

8 CMOS Inverter OFF ON OFF +V (H = 1) V in Q1Q1 Q2Q2 V out 0 (L)ONOFF1 (H) OFFON0 (L) +V (H = 1) (L = 0) 8

9 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LL LH HL HH (L = 0) (H = 1) 9

10 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LH HL HH (L = 0) (H = 1) 10

11 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HL HH (L = 0) (H = 1) 11

12 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HLOFFON OFFH HH (L = 0) (H = 1) 12

13 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HLOFFON OFFH HH ON L (L = 0) (H = 1) 13

14 CMOS NOR Gate 311_0714

15 311_07 Noise Margin V OHmin V IHmin V OLmax V ILmax 15

16 NM H = V OHmin - V IHmin = 4.4 V - 3.15 V = 1.25 V NM L = V ILmax - V OLmax = 1.35 V - 0.1 V = 1.25 V Electrical Characteristics 311_0716

17 311_0717 Propagation Delay

18 311_0718 Propagation Delay

19 Summary  NAND and NOR Gates  DeMorgan's Laws  SOP to NAND-NAND  MOSFETs  CMOS Logic Gates Inverter, NAND, NOR  Electrical Characteristics Noise Margin Propagation Delay 311_0719

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