1. G. Aglieri, P.Jarron, J. Kaplon, A. Kluge, M. Morel, M. Noy, L. Pertktold, K. Poltorak August 27, 2012

2. Aug 27, 2012 Outline Description of base line functionality Description of base line functionality And backup functions And backup functions Data transmission Data transmission Status of individual blocks and assembly Status of individual blocks and assembly A. Kluge2

3. Aug 27, 2012

4. simplified TDCpix A. Kluge4

5. Aug 27, 2012 Main data path, serial read-out A. Kluge5

6. Aug 27, 2012 Parallel read out A. Kluge6

7. Aug 27, 2012 TDC serial read-out A. Kluge7

8. Aug 27, 2012 Bandgap override A. Kluge8

9. Aug 27, 2012 Components with no backup A. Kluge9

10. Aug 27, 2012 Clk modes A. Kluge10 serialPLL2.4 lowClkSync serialPLL2.4 highClkSync serialPLL3.2ext320lowCl kSync ext320highC lkSync ext480lowCl kSync ext480highC lkSync pllOverride #01234567 code001110000110001100H110H0H100H0H110H1H100H11011H0 clkInDigital320 480 320 clkPLL2400 3200----320 clkSync24048032016032024048032 clkFIFOread40 5327 40 5.3 clkMultiSeria l 480 640320 480 64 clkConfig320 240 320

11. Aug 27, 2012 Serial transmission data rate 20 MHz  2.4 Gbit/s  40 Mwords/s (+21% (132 Mhits/s); + 54% (104 Mhits/s) 20 MHz  2.4 Gbit/s  40 Mwords/s (+21% (132 Mhits/s); + 54% (104 Mhits/s) 27 MHz  3.2 Gbit/s  53 Mwords/s (+60% (132 Mhits/s); + 104% (104 Mhits/s) 27 MHz  3.2 Gbit/s  53 Mwords/s (+60% (132 Mhits/s); + 104% (104 Mhits/s) A. Kluge11 Clock divider 2.4/3.2 GHz 1.2/1.6 GHz serial mux & shift (/2) 40/53 MHz parallel_load (/60) 240/320 MHz (/10) Fifo read clkSync 2.4/3.2 GHz 20 MHz PLL

12. Aug 27, 2012 Parallel data transmission (multi serial, 48 bits) 48 bits (not 8b10); 4 I/O pairs 48 bits (not 8b10); 4 I/O pairs Input frequency comes from PLL or from outside Input frequency comes from PLL or from outside Several modes: Several modes: mode serialPLL2.4&ext480: clkFIFOread = 40 MHz  clkMultiSerial = 480 MHz mode serialPLL2.4&ext480: clkFIFOread = 40 MHz  clkMultiSerial = 480 MHz 40 Mhits/s  (21 % (132 Mhits/s) +54 % (104 Mhit/s) 40 Mhits/s  (21 % (132 Mhits/s) +54 % (104 Mhit/s) mode serialPLL3.2: clkFIFOread = 53 MHz  clkMultiSerial = 640 MHz mode serialPLL3.2: clkFIFOread = 53 MHz  clkMultiSerial = 640 MHz 53Mhits/s  (+60% (132 Mhits/s); + 104% (104 Mhits/s) 53Mhits/s  (+60% (132 Mhits/s); + 104% (104 Mhits/s) mode ext320: clkFIFOread = 27 MHz  clkMultiSerial = 320 MHz mode ext320: clkFIFOread = 27 MHz  clkMultiSerial = 320 MHz 27 Mhits/s  (-19 % (132 Mhits/s) +3 % (104 Mhit/s)) 27 Mhits/s  (-19 % (132 Mhits/s) +3 % (104 Mhit/s)) mode PLLoverride:clkFIFOread = 5.3 MHz  clkMultiSerial = 64 MHz mode PLLoverride:clkFIFOread = 5.3 MHz  clkMultiSerial = 64 MHz 5.3 Mhits/s  (-96 % (132 Mhits/s) -95 % (104 Mhit/s)) 5.3 Mhits/s  (-96 % (132 Mhits/s) -95 % (104 Mhit/s)) mode serialTDC mode serialTDC A. Kluge12

13. Aug 27, 2012 Status of blocks and assembly A. Kluge13

14. Aug 27, 2012 TDCpix digital layout A. Kluge14 Assembly & power distribution & IO ring

15. Aug 27, 2012 Quarter chip A. Kluge15

16. Aug 27, 2012 Configuration & dll clk & reset distributor A. Kluge16

17. Aug 27, 2012 Reference digital A. Kluge17

18. Aug 27, 2012 Reference analog A. Kluge18

19. Aug 27, 2012 Temperatur sensor A. Kluge19

20. Aug 27, 2012 IO pads A. Kluge20

21. Aug 27, 2012 IO ring & power distribution A. Kluge21

22. Aug 27, 2012 Data transmission A. Kluge22

23. Aug 27, 2012 Link synchronisation sequence Initiated upon Initiated upon reset from pin (Sequence of 65536 synch words) reset from pin (Sequence of 65536 synch words) reset_cmd command (Sequence of 65536 synch words) reset_cmd command (Sequence of 65536 synch words) send_k_sync_requ command (as long as the command is active) send_k_sync_requ command (as long as the command is active) Each synchronisation word consists of: Each synchronisation word consists of: 6*10 bit characters are sent. 6*10 bit characters are sent. Each 6* 10 bit character is 5* K28.5 symbols followed by one K27.7. Each 6* 10 bit character is 5* K28.5 symbols followed by one K27.7. A. Kluge23

24. Aug 27, 2012 Data transmission Idle command Idle command If no data is transmitted or no frame word is transmitted If no data is transmitted or no frame word is transmitted the idle command is sent over the link. the idle command is sent over the link. It is identical to the link synchronisation word and consists of 5 K28.5 symbols followed by one K27.7 It is identical to the link synchronisation word and consists of 5 K28.5 symbols followed by one K27.7 A. Kluge24

25. Aug 27, 2012 Data transmission: frame word Every time coarse counter rolls over after 2048 clk_dll cycles a frame word is sent at the next available word slot. Every time coarse counter rolls over after 2048 clk_dll cycles a frame word is sent at the next available word slot. clk_dll frequency where the coarse counter and the frame counter is advanced can in principle be different from the clk_sync frequency. clk_dll frequency where the coarse counter and the frame counter is advanced can in principle be different from the clk_sync frequency. The time intervall between two frames depends mainly on clk_dll. However, once a frame request is initiated in the clk_dll domain, this request is ported into the clk_sync domain and is executed at the next word transmission cycle which has a period of 6 clk_sync cycles. The time intervall between two frames depends mainly on clk_dll. However, once a frame request is initiated in the clk_dll domain, this request is ported into the clk_sync domain and is executed at the next word transmission cycle which has a period of 6 clk_sync cycles. Thus in nominal conditions (clk_sync & clk_dll = 320 MHz) the frame is sent out in average each (1/320 MHz * 2048 =) 6.4 µs. However as 2048 cycles cannot be divided 6 (number of 8b10b words in each data word) the number of word transmission cycles between two frame words toggles between 341 and 342 (2 * 341 and 1 *342 or 2 * 6.39375 µs and 6.4125 µs). Thus in nominal conditions (clk_sync & clk_dll = 320 MHz) the frame is sent out in average each (1/320 MHz * 2048 =) 6.4 µs. However as 2048 cycles cannot be divided 6 (number of 8b10b words in each data word) the number of word transmission cycles between two frame words toggles between 341 and 342 (2 * 341 and 1 *342 or 2 * 6.39375 µs and 6.4125 µs). The frame word is defined as follows: The frame word is defined as follows: word_frame0(27 downto 0)<= frame_counter; word_frame0(27 downto 0)<= frame_counter; word_frame0(36 downto 28)<= hit_counter; word_frame0(36 downto 28)<= hit_counter; word_frame0(42 downto 37)<= qchip_collision_count; word_frame0(42 downto 37)<= qchip_collision_count; word_frame0(46 downto 43)<= “0000” not used; word_frame0(46 downto 43)<= “0000” not used; word_frame0(47)<= '1';--format bit word_frame0(47)<= '1';--format bit A. Kluge25

26. Aug 27, 2012 Data transmission: frame word --(47) status bit1 bit --(47) status bit1 bit --(46..43)not used = ‘0‘4 bit --(46..43)not used = ‘0‘4 bit --(42..37) # of collisions in previous frame6 bits --(42..37) # of collisions in previous frame6 bits 2**6=64, 3.3 MHz*10*6.4us=211hits --> count to 64 allows 1/3 of hits to collide 2**6=64, 3.3 MHz*10*6.4us=211hits --> count to 64 allows 1/3 of hits to collide --(36..28) # of hits in previous frame9 bits --(36..28) # of hits in previous frame9 bits hits per qchip and frame= 130 Mhits/s/4*6.4us=208-> hits per qchip and frame= 130 Mhits/s/4*6.4us=208-> max hits in frame: worst case: clk_dll = 240 MHz clk_sync = 320MHz clk serial 3200 MHz-> number of -> 2048 / 240 MHz = 8.53 us frame length -> transmission cycles in one frame : 8.53 us *(3200MHz / 60)= 455 -> 9 bit max hits in frame: worst case: clk_dll = 240 MHz clk_sync = 320MHz clk serial 3200 MHz-> number of -> 2048 / 240 MHz = 8.53 us frame length -> transmission cycles in one frame : 8.53 us *(3200MHz / 60)= 455 -> 9 bit --(27..0) framecounter28 bit --(27..0) framecounter28 bit 2**28*6.4us=1718s 2**28*6.4us=1718s A. Kluge26

27. Aug 27, 2012 Data transmission: data word The data word is sent whenever a hit is available and no word with higher priority needs to be sent. The data word is sent whenever a hit is available and no word with higher priority needs to be sent. The data word is defined as follows: The data word is defined as follows: (47) Status/data selector1 bit (47) Status/data selector1 bit (46..40) Address7 bit(90 pixel groups) (46..40) Address7 bit(90 pixel groups) (39..35) Address-hit arbiter5 bit (39..35) Address-hit arbiter5 bit (34..30) Address pileup5 bit (34..30) Address pileup5 bit (29) Leading coarse time selector1 bit (29) Leading coarse time selector1 bit (28..17) Leading coarse time12 bit (28..17) Leading coarse time12 bit 1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs 1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs (16..12) Leading fine time5 bit98 ps -> 3.125 ns (16..12) Leading fine time5 bit98 ps -> 3.125 ns (11) Trailing coarse time selector 1 bit (11) Trailing coarse time selector 1 bit (10..5) Trailing coarse time6 bit64*3.125 ns = 200 ns (10..5) Trailing coarse time6 bit64*3.125 ns = 200 ns (4..0) Trailing fine time5 bit98 ps -> 3.125 ns (4..0) Trailing fine time5 bit98 ps -> 3.125 ns A. Kluge27

28. Aug 27, 2012 Data type The word transmission priority is defined as follows: The word transmission priority is defined as follows: send_k_sync_slot_requ (user request) send_k_sync_slot_requ (user request) send_testpattern_requ (user request) send_testpattern_requ (user request) send_k_word_request (user request) send_k_word_request (user request) send_serial_time_requ (user request) send_serial_time_requ (user request) send_frame_requ send_frame_requ send_data_requ send_data_requ A. Kluge28

29. Aug 27, 2012 Configuration register Operation modes and Configuration register Operation modes and Configuration register --configuration register --configuration register send_k_sync_requ<= configuration_data_int_in(0); default = ‘0’ send_k_sync_requ<= configuration_data_int_in(0); default = ‘0’ send_k_word_requ<= configuration_data_int_in(1);default = ‘0’ send_k_word_requ<= configuration_data_int_in(1);default = ‘0’ k_word_type<= configuration_data_int_in(5 downto 2); default = “0000” k_word_type<= configuration_data_int_in(5 downto 2); default = “0000” enable_serial_time_int<= configuration_data_int_in(6);default = ‘0’ enable_serial_time_int<= configuration_data_int_in(6);default = ‘0’ enable_test_pattern_int<= configuration_data_int_in(7);default = ‘0’ enable_test_pattern_int<= configuration_data_int_in(7);default = ‘0’ new_data_testpattern<= configuration_data_int_in(8); default = ‘0’ new_data_testpattern<= configuration_data_int_in(8); default = ‘0’ --> new_data_testpattern acts as write command for the data_testpattern fifo, --> new_data_testpattern acts as write command for the data_testpattern fifo, --> each 01 transition is used as write cmd --> each 01 transition is used as write cmd A. Kluge29

30. Aug 27, 2012 Configuration register (2) data_testpattern<= configuration_data_int_in(62 downto 9); default = “00..00” data_testpattern<= configuration_data_int_in(62 downto 9); default = “00..00” --> Data_testpattern is composed of two words: --> Data_testpattern is composed of two words: --> word_test_pattern_int word_test_pattern_int<= data_testpattern (47 downto 0); --> are 6 times 8 bit characters composing the 48 qchip_word, --> are 6 times 8 bit characters composing the 48 qchip_word, --> K_word is a 6 bit word indicating whether the 6 characters are to be treated as data or k character. --> K_word is a 6 bit word indicating whether the 6 characters are to be treated as data or k character. --> k_word_test_pattern k_word_test_pattern<= data_testpattern (53 downto 48); --54 bit: data_testpattern -> write data into cell 54 of data_testpattern --54 bit: data_testpattern -> write data into cell 54 of data_testpattern --> subsequent writing moves write pointer of FIFO so that all 8 FIFO cells can be written --> subsequent writing moves write pointer of FIFO so that all 8 FIFO cells can be written --> when test pattern is enabled, all 8 FIFO cells are read subsequently and pushed into --> when test pattern is enabled, all 8 FIFO cells are read subsequently and pushed into --> the data stream, thus the data stream consists of a multiple of 8 data words. --> the data stream, thus the data stream consists of a multiple of 8 data words. A. Kluge30

31. Aug 27, 2012 TDC serial read-out The 32 bit to 5 bit encoder, group and column FIFOs in the TDCs are not used. The 32 bit to 5 bit encoder, group and column FIFOs in the TDCs are not used. Instead the two 32 bit fine registers and the 52 bit coarse register of one TDC channel are chained together. Instead the two 32 bit fine registers and the 52 bit coarse register of one TDC channel are chained together. In each quarter chip there are 90 TDC channels and thus 90 serial TDC chains. Each of these chains indicates a new data set by activating its serial_holding bit. In each quarter chip there are 90 TDC channels and thus 90 serial TDC chains. Each of these chains indicates a new data set by activating its serial_holding bit. Serial chains are multiplexed into serial & parallel read-out Serial chains are multiplexed into serial & parallel read-out A. Kluge31

32. Aug 27, 2012 ASIC status by Gianluca

33. Aug 27, 2012 NA62 GTK WG 28/8/2012 - TDCpix status Outline by Gianluca Progress since last status report (17 Jul 2012) Status Road ahead

34. NA62 GTK WG 28/8/2012 - TDCpix status Analog blocks Implementation of Serializers  Issue with fast load signals skew discovered  Solutions being explored and checked by simulation

35. NA62 GTK WG 28/8/2012 - TDCpix status Digital blocks Gianluca Aglieri Rinella

36. NA62 GTK WG 28/8/2012 - TDCpix status Top level Power de-coupling Need of significant on-chip power decoupling capacitance identified Need of significant on-chip power decoupling capacitance identified  Specially relevant for digital power domain  Addition of on-chip capacitor implies re-spin of implementation of some blocks  Analog and DLL power domains already including significant decoupling

37. NA62 GTK WG 28/8/2012 - TDCpix status Status at a glance on 6 Feb 2012

38. NA62 GTK WG 28/8/2012 - TDCpix status Status at a glance 22 May 2012

39. NA62 GTK WG 28/8/2012 - TDCpix status Status at a glance 17 July 2012

40. NA62 GTK WG 28/8/2012 - TDCpix status Status at a glance 28 Aug 2012

41. Aug 27, 2012 Status Present work: Present work: Progress on design and implementation of all building block Progress on design and implementation of all building block Stand-alone functional &sign-off verification for all blocks in progress Stand-alone functional &sign-off verification for all blocks in progress Iteration of engineering changes in serializer circuits Iteration of engineering changes in serializer circuits Top level EoC and IO and power pad placement first version completed Top level EoC and IO and power pad placement first version completed Assembly of TDCpix digital & DRC & LVS Assembly of TDCpix digital & DRC & LVS A. Kluge41

42. Aug 27, 2012 NA62 GTK WG 28/8/2012 - TDCpix statusStatus Future work: Future work: Complete stand-alone sign-off verification for individual blocks Complete stand-alone sign-off verification for individual blocks Re-spin implementation of TDC adding decoupling capacitance Re-spin implementation of TDC adding decoupling capacitance Complete implementation of top level: TDCpix digital & analog  TDCpix_top Complete implementation of top level: TDCpix digital & analog  TDCpix_top I/O and power pad ring refinements I/O and power pad ring refinements Signal routing Signal routing Power distribution Power distribution Sign-off checks Sign-off checks Powering, DRC, LVS, Antenna in TDCpix_top Powering, DRC, LVS, Antenna in TDCpix_top Functional verification of the full chip by simulation on final netlist Functional verification of the full chip by simulation on final netlist functional verification of TDCpix_top_digital & functional verification of TDCpix_top_digital & functional verification of TDCpix_top functional verification of TDCpix_top