1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 4 Andy Schellin

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Tasks/Workflow -Optimization of Synopsys results -Layout -Floorplanning, Placement, Routing -Improvements

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Floorplanning

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Best Metric

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Cadence Layout -Aspect-Ratio: 3 -Timing Driven: high effort -Optimize Design: -Leakage Power Effort: high -Dynamic Power Effort : high -Possible improvements -New order of output pins -Placement by hand in critical areas

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Mandatory infos for layout Timing (f max / T min )409MHz / 2,44ns Power (P dyn / P leak )952µW/13,4nW Core size [µm²] 2720 Core utilization73,7% # Pipeline stages2 Metric [1/J²] 1,31*10 28 Slide 6

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Layout with pads -Total Dynamic Power: 44,46mW -Cell Leakage Power: 6,27mW -99,73% power loss through pads

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention Slide 8