1. TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK

2. Probe for SPI / I 2 C TPMOSI TPSCLK TPMISO TPSEL1 TPSEL0 TPSDA TPSCL NOTE : U35 is I2C Bus Isolator

3. Probe for IPM Bus TPSDAB TPSCLB TPSDAA TPSCLA NOTE : U5 (bottom) is I2C Bus Isolator for IPMB A U6 (top) is I2C Bus Isolator for IMPB B

4. Probe for GND TPG3 TPG5 TPG6 TPG2 TPG1 TPG4

5. Probe driven by FPGA TP1_2 TP2_2 TP3_2 TP1_1 TP2_1 TP3_1 NOTE : TP1, 2, and 3 are connected to AD3, AD4, and AD2, respectively.

6. Power distribution (1) PIM In : 48V Out : 3.3V & -48V Power Converter In : -48V Out: VCC12 U16 In : VCC12 Out : VCC3V3 (20A) U17 In : VCC12 Out : VCC1V0 (20A)

7. Power distribution (2) U22 In : VCC1V8 Out : VDDR1 (1.5V) (3A, linear) U32 In : VCC1V8 Out : VDDR2 (1.5V) (3A, linear) U29 In : VCC3V3 Out : VCC2V5 (3A, linear) U18 In : VCC12 Out : VCC1V8 (10A) U23 In : VCC12 Out : MGTAVTT (10A) U21 In : VCC12 Out : MGTAVCC (10A)

8. U17 U16 117 118 121 120 VCC12 @U16, U17

9. VCC3V3 @U29 U29 157 VCC3V3

10. MGTAVCC (1.0V) @U21 U21 86896576 MGTAVCC

11. MGTAVTT (1.2V) @U23 13290122105 MGTAVTT U23

12. 20 3.3V (management) 19 3.3V (management) Management 3.3V @ PIM

13. 66_1 68_1 67_1 67_2 66_2 68_2 VCC1V8 VCC1V8@FPGA

14. VDDR1@U22 VDDR2@U32 Pin5 or Pin4. Pin5 looks easier to avoid short with PIn3 of GND U22 U32

15. 55_2 75_2 155_2 115 53_2 60_2 53_1 55_1 54_1 75_1 54_2 59_1 VCC3V3 VCC1V0 VCC3V3 56_1 56_2 156_1 155_1 156_2 60_2 59_2 VCC2V5 VCC1V0 VCC3V3 Polarized Capacitors (330uF, Yellow big ones) VCC1V8

16. Polarized Capacitors around PIM C40 (470uF), C35, C36 (120uF) They have to have bar on downside as shown below

17. Chip Orientation with Tiny dot silkscreened on board (examples)

18. CLOCK setting U27=GTXREFCLK U11=SYSCLK Typical Setting 125 MHz {1, 0, 1, 1, 0, “X”} 00 11 00 11 150 MHz {0, 0, 1, 1, 0, “X”} 200 MHz {0, 0, 0, 1, 0, “X”} 156.25 MHz {1, 0, 1, 1, 0, “X”}