1. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Commissioning, operation and first physics results of the CDF Run2a Silicon and status of its future upgrade for Run2b Gino Bolla Purdue University For CDF RUN2 Silicon Group

2. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany CDF RunII (The need for a strong tracker) lPhysics with 2-9 fb-1  Precise Measurements of M top and M W  CP violation, B s mixing  More … lB,C quarks tagging is crucial  Long lifetime (mm to cm) lVertex finding  High impact parameter resolution lEfficient trigger  SVT (secondary Vertex Trigger)  Fast (@L2) displaced tracks trigger. COT 30240 ch, 96 layer drift chamber  (1/p T ) ~ 0.1%/GeV  (hit) ~ 150  m SVXII + ISL + L00 7-8 silicon layers 722000 ch r , rz views z 0 max =45 cm,  max =2 1.3<R<30cm

3. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany A top candidate lTypical travel distances:  Bottom: 5 mm  Charm: 1 mm lImpact parameter resolution  ~35  m in   Will improve by using L00

4. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany CDF Silicon (What does it look like) 1 layer (L00) very close to the beam: improve IP res. & b-tagging Use L00/SVXII for vertexing & trigger: high density & precise alignment crucial! Use ISL for tracking: simpler design; precise alignment not so important x [cm] y [cm] HIGHLIGHTS: High speed Dead-timeless operation Displaced track trigger L00 ISL SVXII 1 central / 2 forward layers (ISL) at large radius: tracking 5 layers (SVXII) very compact in r, ,z: 3D vertexing & tracking

5. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany 6 electrical barrels Z SVXII the center piece l5 double sided layers  3 x 90 o and 2 x 1.2 o lVery compact lTight alignment tolerances  For the trigger lVery symmetric lMany (maybe too many) different components 2.5 cm 10.6 cm x y Note “wedge” symmetry

6. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany ISL on the outside and L00 on the inside  One central layer  Link tracks from COT to SVXII  Two forward layers (~2 m long)  Extend tracking up to |  |=2 (COT stops at 1)  Simpler design  Not used on the trigger (relaxed alignment)  Hybrids mounted OFF silicon  A single flavor  Lot of space (compared to SVXII) lightweight signal & bias cables (Kapton) sensors cooling tube SVXII inner bore 2.3cm 4.2cm Be beampipe Precision position measurement before scattering  One SS layer on the Beam pipe  25  m pitch (50  m readout)  Low material budget  High Radiation  Actively cooled LHC-like sensors  Electronic at larger radii ISL L00

7. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany The heart of it all (the SVX3d chip) 128 channels 46 pipeline cells Fabricated in the Honeywell 0.8  m rad.hard process äAnalog Front End (FE) and Digital Back End (BE): - Compatible with 396/132 nsec bunch spacing - FE has relatively low noise integrator with 128 channels and 46 cell analog pipeline with 4 buffer cells - BE has comparator, 8-bit Wilkinson ADC, and sparse readout with neighbors logic äDead-timeless: ;Capable of analog operations during digitization and readout äDynamic pedestal subtraction: - Enables on-chip common mode noise suppression

8. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Same data but different code Integration and Commissioning A long list of troubles to deal with  Most of them specific to the CDF system  Others are of common interest A good monitoring strategy  First look at the whole thing as a piece of hardware  Second look at it as a particle detector Now 90+% is producing good data for physics Large effort on the offline as well  Clustering  Alignment  Tracking algorithms Wire-bonds with current in the 100 mA range if pulsed at the right frequency can oscillate due to small (10-50 mg) Lorentz forces because resonance behaviors can be excited. Fatigue induces cracks on the heel and the electrical continuity is lost

9. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Performance (1) resolution 9m9m Residual [  m] Charge [ADC] charge collectio n z side charge [ADC]  side charge [ADC] charge correlatio n Single hit Efficiencies~99 % S/N >10 dE/dx particle identification

10. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Performance (2) Measurements using triggered J/Psi candidate events since January 2003 shutdown. No background subtraction is performed. A further 3 % increase on efficiency is expected Performing a background subtraction (about 1%). Improvements of ISL alignment and retuning of the the tracking road sizes (about 2 %) Average tracking Efficiency is 87.8 ± 0.1 (stat)% Average fake rate is 1.7 ± 0.4 (stat)%

11. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Performance (3) At a higher level things get more complicated lB-tagging efficiencies in the 40-50 %  Visible degradation of performances in the regions between barrels lWill improve in the future  Adding L00 will help in between barrels   coverage will increase by using ISL Lots of CDF physics talks at this conference

12. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany SVT (Secondary Vertex Trigger) lInput (L1A ~10-40 KHz)  Outer drift chamber trajectories  Silicon pulse height for each channel Output (~ 20  s later)  Trajectories that use silicon hits l150 VME boards  Find and fit silicon tracks with ~ offline accuracy In 15 microseconds look for 2 tracks with impact parameters > 120  m primary vertex secondary vertex impact parameter a few mm 2.5 MHz 25 kHz 250 Hz 50 Hz L1: 5.5  s, synchronous, fast programmable logic (CAL, , COT tracks) L2: ~30  s, asynchronous, programmable logic + CPU (jets, silicon tracking) L3: ~200 PCs spend ~1s/event on ~full reco (full-precision tracking, form masses, etc.) ~140 separate trigger paths (e, , ,, , jet, displaced track, b-jet, …)

13. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany SVT performance -500 -250 0 250 500 SVT impact parameter (  m) 35  m  33  m resol  beam   = 48  m 0 10 20 30 40 50 SVT latency (  s) 24  s 0  2  +500 -500 0 d (  m) vs  (raw) d (  m) vs  (subtracted) +500 -500 0

14. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany A paper with only 12 pb -1 lResults: M(D s ) – M(D + )  99.41 + 0.38 + 0.21 MeV/c 2  PDG: 99.2+0.5 MeV/c 2

15. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany What is there ahead of us Until the LHC turn-on, the Fermilab Tevatron has the highest energy collisions and is the only place to search for the Higgs and other new particles. The Run II Physics Program extends to 5-15 fb -1. Expected life of the Run IIa Silicon detector ~ 4-5 fb -1. Run IIb Silicon Detector replaces the inner 6 layers with an improved and radiation tolerant detector. Need to be built in a very tight schedule

16. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany The CDF Run2b Silicon Layer 0: 12 fold Axial Layer 1: 6 fold Axial-Axial Layer 2: 12 fold Axial-Stereo (1.2 o ) Layer 3: 18 fold Axial-Stereo (1.2 o ) Layer 4: 24 fold Axial-Stereo (1.2 o ) Layer 5: 30 fold Axial–Axial Improvements in RunIIb Design:  Rad hard RO chips (0.25  m technology) Extension of the “contained b-jets” region (active length = 1.2 m vs 0.9m in RunIIa) larger and more uniform radial distribution (R= 2.1 – 16.4 cm compared to 1.3-10.6cm in RunIIa) Good impact parameter resolution with low mass L0 design Strengthened inner tracking - redundant axial layers at L1 Larger radius outer staves - better connection to ISL Fewer component parts: 4-chip hybrids used on 93% of staves

17. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Run2b Silicon prototype stave prototype barrel Well advanced project the SVX4 chip works! the stave concept works! prototyping of most components ~finished most parts well in time Laser test ped+signal pedestal subtracted signal Channel # ADC

18. G. Bolla, Purdue University for the CDF RUN2 Silicon EPS (July 17 th -23 rd 2003), Aachen, Germany Summary lThe CDF silicon detector is doing its job and produces good data necessary for the physics program of the experiment  A lot of struggling during the commissioning  A well organized maintenance plan in place lThe innovative Fast displaced tracks trigger is enhancing the experiment capabilities lStill work to be done to fully exploit the Si capabilities (L00 and ISL on the offline analysis) lThe TeV program extends over the lifetime of the existing hardware lTo fully explore the potential for new physics at CDF the RUN2b silicon is approaching its production phase.