1. COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals

2. Outline  Behavioral Modeling  Boolean Equation-Based Behavioral Models of Combinational Logic  Assign Statement  Verilog Operators  Propagation Delay & Continuous Assignment  Behavioral Description of an Adder

3. Behavioral Modeling  Behavioral modeling describes the functionality of a design  What the design will do  Not how the design will be built in hardware  Behavioral models specify the input-output model of a logic circuit and suppress details about its low level internal structure.  Behavioral modeling encourages designers to  Rapidly create a behavioral prototype of a design  Verify its functionality  Use synthesis tool to optimize and map design into a given technology

4. Data Types for Behavioral Modeling  All variables in Verilog have a predefined type.  There are two families of data types: nets and registers.  Net variables act like wires in physical circuit and establish connectivity between design objects.  Register variables act like variables in ordinary procedural languages – they store information while the program executes.  Register types include: reg, integer, real, realtime, time.  A wire and a reg have a default size of 1 bit.  Size of integer is the size of word length in a computer, at least 32.

5. Boolean Equation-Based Behavioral Models of Combinational Logic  A Boolean equation describes combinational logic by an expression of operations on variables.  In Verilog, this is done by continuous assignment statement.  Example: module AOI_5_CA0 ( input x_in1, x_in2, x_in3, x_in4, x_in5, output y_out); assign y_out = !( (x_in1 && x_in2) || (x_in3 && x_in4 && x_in5) ); endmodule

6. Assign Statement  The keyword assign declares a continuous assignment.  It associates the Boolean expression on the RHS (right hand side) with the variable on the LHS (left hand side).  The assignment is sensitive to the variables in the RHS.  Any time an event occurs on any of the variables on the RHS, the RHS expression is revaluated and the result is used to update the LHS.

7. Integer Numbers in Verilog  constant numbers can be specified in decimal, hexadecimal, octal, or binary format  integer numbers can be specified as:  Syntax: ' (size is in number of bits)  Sized or unsized numbers ( Unsized size is 32 bits )  In a radix of binary, octal, decimal, or hexadecimal  Radix and hex digits (a,b,c,d,e,f) are case insensitive  Spaces are allowed between the size, radix and value  The character (_) is legal anywhere in a number except as the first character (e.g. 12'b1011_1100_0010, 'hA8, 8'd15)  When is smaller than, then left-most bits of are truncated

8. Verilog Operators { }concatenation + - * / ** arithmetic %modulus > >= < <= relational !logical NOT && logical AND ||logical OR ==logical equality !=logical inequality === case equality !== case inequality ? :conditional ~bit-wise NOT &bit-wise AND |bit-wise OR ^bit-wise XOR ^~ ~^bit-wise XNOR &reduction AND |reduction OR ~&reduction NAND ~|reduction NOR ^reduction XOR ~^ ^~reduction XNOR <<shift left >>shift right

9. Verilog Operators  Arithmetic Operators:  Each operator takes two operands. + and – could also take a single operand  During synthesis, the + and - operators infer an adder and a subtractor  Xilinx XST software can infer a block multiplier during synthesis for the multiplication operator  /, %, and ** operators usually cannot be synthesized automatically  Shift operators: Four shift operators  >>, << logical shift right and left (0s inserted from the right or the left)  >>>, >> operation and 0's are shifted in for the <<< operation)

10. Verilog Operators  If both operands of a shift operator are signals, as in a << b, the operator infers a barrel shifter, a fairly complex circuit  If the shifted amount is fixed, as in a << 2, the operation infers no logic and involves only routing of the input signals (can also be done with {} operator)  Examples of shift operations:

11. Verilog Operators  Relational and equality operators:  Compare two operands and return a 1-bit logical (Boolean) value: either 0 or 1  4 relational operators: >, =  Equality operators: ==, ! =,  The relational operators and the == and ! = operators infer comparators during synthesis

12. Verilog Operators  Bitwise operators:  4 basic bitwise operators: & (and), I (or), ^ (xor), and ! (not)  The first three operators require two operands  Negation and xor operation can be combined, as in ~^ or ^~ to form the xnor  operations are performed on a bit-by-bit basis  Ex.: let a, b, and c be 4-bit signals: i.e. wire [3:0] a, b, c ; The statement:assign c = a I b ; is the same as:assign c[3] = a[3] I b[3]; assign c[2] = a[2] I b[2]; assign c[1] = a[1] I b[1]; assign c[0] = a[0] I b[0];

13. Verilog Operators  Reduction operators: &, I, and ^ operators may have only one operand and then are known as reduction operators.  The single operand usually has an array data type.  The designated operation is performed on all elements of the array and returns a I-bit result.  For example, let a be a 4-bit signal and y be a 1-bit signal: wire [3:0] a ; wire y ; The statement: assign y = I a ; // only one operand is the same as:assign y = a[3] | a[2] | a[1] | a[0] ;

14. Verilog Operators  Logical operators: && (logical and), II (logical or), and ! (logical negate)  operands of a logical operator are interpreted as false (when all bits are 0's) or true (when at least one bit is 1), and the operation always returns a 1-bit result  Usually used as logical connectives of Boolean expressions,  bitwise and logical operators can be used interchangeably in some situations.  Examples of bitwise and logical operations

15. Verilog Operators  Conditional operator: ? : takes three operands and its general format is [signal] = [boolean-exp] ? [true-exp] : [false-exp];  The [boolean-expl] is a Boolean expression that returns true (1) or false ( 0).  Ex.: assign max = (a>b) ? a : b; //max will get the maximum of the signals a and b  The operator can be thought of as a simplified if-then-else statement.  Can be cascaded or nested

16. Verilog Operators  Concatenation operator: { }  { } combines segments of elements and small arrays to form a large array: wire [7:0] a, rot, shl, sha; assign rot = {a[2:0], a[7:3]} ; // Rotate a to right 3 bits assign shl = {3'b000, a[7:3]} ; // shift a to right 3 bits and insert 0s (logical shift) assign sha = {a[7], a[7], a[7], a[7:3]} ; // arithmetic shift a to right 3 bits

17. Full Adder module fadd (output Cout, S, input A, B, Cin); assign S = A ^(B ^ Cin); assign Cout = (A & B) | (A & Cin) | (B & Cin) ; endmodule

18. Propagation Delay & Continuous Assignment  Propagation delay can be associated with a continuous assignment so that its implicit logic has same functionality and timing characteristics as its gate level implementation. module fadd (output Cout, S, input A, B, Cin); assign #6 S = A ^(B ^ Cin); assign #5 Cout = (A & B) | (A & Cin) | (B & Cin); endmodule

19. Behavioral Description of an Adder module adder #(parameter width = 4) (output cout, output [width-1:0] sum, input [width-1:0] a, b, input cin); assign {cout, sum} = a + b + cin; // note: Verilog treats wires as ‘unsigned’ numbers endmodule { Cout, S } is a 5 bit bus: Cout S[3] S[2] S[1] S[0] 4-bit operands, 5-bit result