1. Delivering Success. Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66 By Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch Device Modeling Department, SILTERRA Malaysia Sdn. Bhd. 2007

2. Delivering Success. ESSDERC 2007 MUNICH 2 Outline Aurora and HSPICE Level 66 Background 32V Asymmetric HV MOS Background Modeling Flow for Asymmetric HV MOS Results and Discussion Self Heating Effect in HV MOS Conclusion

3. Delivering Success. ESSDERC 2007 MUNICH 3 Aurora and HSPICE Level 66 Background Aurora oproduct of Synopsys Inc for Modeling. oBeside HSPICE Level 66, Aurora also offers all types of models that normally offered by other products. Contends for the modeling and SPICE simulation of digital CMOS, analog and RF circuit that operates up to 100V.

4. Delivering Success. ESSDERC 2007 MUNICH 4 Aurora and HSPICE Level 66 Background (cont’d) HSPICE Level 66 is a proprietary product of Synopsys. HSPICE Level 66 model oself heating, forward and reverse mode, asymmetric parasitic, and bias dependent RDS- based on BSIM4 oprimarily targets for LDMOS (Lateral Double Diffused MOSFET) and EDMOS (Extended Drain MOSFET) device technologies.

5. Delivering Success. ESSDERC 2007 MUNICH 5 32V Asymmetric HV MOS Background (cont’d) Structure

6. Delivering Success. ESSDERC 2007 MUNICH 6 Modeling Flow For Asymmetric HV MOS Golden Die Asymmetric Behavior Checking DC Measurement AC Measurement Aurora Extraction And Optimization Hspice Simulation

7. Delivering Success. ESSDERC 2007 MUNICH 7 Modeling Flow For Asymmetric HV MOS (cont’d) Asymmetric Behavior Checking Purpose - check the asymmetric effect of the transistor. Measurement - swapping the bias voltage of source and drain for each measurement. Compare IdVd curve for forward and reverse mode measurement.

8. Delivering Success. ESSDERC 2007 MUNICH 8 Long Channel Device (W/L=25u/25u) Almost similar ID Modeling Flow For Asymmetric HV MOS (cont’d) Asymmetric Behavior Checking +++ forward mode ___ reverse mode

9. Delivering Success. ESSDERC 2007 MUNICH 9 Asymmetric Behavior Checking Short Channel Device (W/L=25u/4.25u) Significant ID decrease +++ forward mode ___ reverse mode VGS

10. Delivering Success. ESSDERC 2007 MUNICH 10 The results showed that shorter length device exhibits quite significant Id decrease for reverse mode measurement while the long channel device exhibits almost similar Id curve for both modes of measurement Modeling Flow For Asymmetric HV MOS (cont’d)

11. Delivering Success. ESSDERC 2007 MUNICH 11 Modeling Flow For Asymmetric HV MOS (cont’d) DC Measurement Measurements: oIdVg@low Vdd with different Vb oIdVg@high Vdd with different Vb oIdVd @Vb=0 with different Vg oIdVd @high Vb with different Vg Before measuring all the modeling devices, Wide Width and small Length transistor with different back biases and different temperatures must be evaluated first

12. Delivering Success. ESSDERC 2007 MUNICH 12 To properly model the effect of asymmetric, the modeling structure for CV need to be designed with extra structures compare to symmetric structure. All the CV modeling structures need to be separated into 2 different structures: o Source design rule o Drain design rule. Thus, the CV measurement for asymmetric transistor is almost double compare to symmetric transistor. Modeling Flow For Asymmetric HV MOS (cont’d) CV Measurement

13. Delivering Success. ESSDERC 2007 MUNICH 13 Extraction strategy – almost similar to BSIM4 The preferred mobility model in Level 66 oMOBMOD=0 Source and Drain parameters are not equal. e.g RSW and RDW, RSWMIN and RDWMIN Both drain side and source side bias dependence parameters of LDD resistance can be optimized. Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization

14. Delivering Success. ESSDERC 2007 MUNICH 14 Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization There are reverse mode parameters available for optimization i.e ETA0I, ETABI, DSUBI oToo many of these parameters are not encouraged. Self heating effect can be turned on by setting SHMOD=1 and RTH0>0. oStrongly advised to set TSHFLAG=1 during the optimization - internal approximation of self heating effect will be used during the optimization. Hence, the speed of the optimization is significantly improved. In the final step, the optimization can be refined by setting TSHFLAG=0. When self heating is turned on, the temperature parameters need to be extracted as much as possible before we do extraction for saturation region parameters.

15. Delivering Success. ESSDERC 2007 MUNICH 15 Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization Disadvantages of Level 66 model: Slower model evaluation -includes internal nodes (solver need to be invoked for every bias point) There is no reliable way to extract thermal capacitance. Thus, we need to develop a method to include thermal time constant in our model.

16. Delivering Success. ESSDERC 2007 MUNICH 16 Results and Discussion W/L = 25um/25um +++ Meas ___ Model

17. Delivering Success. ESSDERC 2007 MUNICH 17 Results and Discussion (cont’d) W/L = 25um/4.25um +++ Meas ___ Model

18. Delivering Success. ESSDERC 2007 MUNICH 18 Results and Discussion (cont’d) W/L = 25um/25um +++ Meas ___ Model

19. Delivering Success. ESSDERC 2007 MUNICH 19 Results and Discussion (cont’d) W/L = 25um/4.25um +++ Meas ___ Model

20. Delivering Success. ESSDERC 2007 MUNICH 20 Results and Discussion (cont’d) Idsat (uA/um)

21. Delivering Success. ESSDERC 2007 MUNICH 21 Results and Discussion (cont’d) Vth (V)

22. Delivering Success. ESSDERC 2007 MUNICH 22 Results and Discussion (cont’d) +++ Meas ___ Model

23. Delivering Success. ESSDERC 2007 MUNICH 23 Results and Discussion (cont’d) +++ Meas ___ Model

24. Delivering Success. ESSDERC 2007 MUNICH 24 Results and Discussion (cont’d) In this paper, IdVg and IdVd curves for 25um/25um and 25um/4.25um have been used to demonstrate model accuracy. The model also correctly simulates self heating effect The model scalability (across W and L) also showed a good agreement with measurement data. Less than 5%. The accuracy of the AC behavior is excellent. Less than 1%.

25. Delivering Success. ESSDERC 2007 MUNICH 25 Self Heating Effect in HV MOSFET HPWELL N-DRIFT POLY STI N+ STI P+ P-Sub N-DRIFT N+ STI HEAT Gate Source Drain If P is moderate(mW), self heating is not severe since it reach its thermal equilibrium with its environment

26. Delivering Success. ESSDERC 2007 MUNICH 26 Experimental setup VGVG 4.7  F 50  VDVD oscilloscope V DD Pulse Gen Self Heating Effect in HV MOSFET (cont’d)

27. Delivering Success. ESSDERC 2007 MUNICH 27 Dynamic response of HV NMOS to typical gate pulse VGVG VDVD Self Heating Effect in HV MOSFET (cont’d)

28. Delivering Success. ESSDERC 2007 MUNICH 28 Self Heating Effect in HV MOSFET (cont’d) R TH extraction R TH will be extracted from Aurora by fitting the data for W=25um and different L. set SHMOD=1 and RTH0>0. This is to ensure that the R TH can be scaled with L.

29. Delivering Success. ESSDERC 2007 MUNICH 29 Transient drain-current characteristics of HV NMOS Due to SHE

30. Delivering Success. ESSDERC 2007 MUNICH 30 Time constant for self heating of HV NMOS

31. Delivering Success. ESSDERC 2007 MUNICH 31 Self Heating Effect in HV MOSFET (cont’d) Extracted time constant and C TH Time constant is extracted from : y = 2.3011e -0.0546x where thermal time constant, R TH C TH = 1/0.0546 = 18.32 us From Aurora extraction R TH = 6.85E-03 mºC/W Hence the extracted thermal capacitance: C TH = 18.32us/R TH = 2.67E-03 (W*sec)/ mºC

32. Delivering Success. ESSDERC 2007 MUNICH 32 Conclusion Modeling strategies for 32V asymmetric HV MOSFET using Aurora and HSPICE level 66 has been presented Model shows: oExcellent DC IV results for entire DC bias range oExcellent behavior of junction capacitances Model scalability (across W and L) also showed good agreement with measurement data. Less than 5% Correctly simulate SHE Extraction of Thermal resistance and capacitance by Pulsed gate measurement

33. Delivering Success. ESSDERC 2007 MUNICH 33 Thank You