1. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 1 Wojciech Dulinski, IPHC Strasbourg on behalf of: Gregory Bertolone,Andrei Dorokhov, Frederic Morel, Xiaomin Wei (Strasbourg), Yavuz Degerli (Saclay), Lodovico Ratti (Pavia) and Valerio Re (Bergamo) on behalf of: Gregory Bertolone, Andrei Dorokhov, Frederic Morel, Xiaomin Wei (Strasbourg), Yavuz Degerli (Saclay), Lodovico Ratti (Pavia) and Valerio Re (Bergamo) Ultra Thin, Fully Depleted MAPS based on 3D Integration of Heterogeneous CMOS Layers (3 Tiers) On the way towards fast, radiation tolerant and ultra thin CMOS sensors, we propose fully depleted epitaxial substrate with first stage buffer amplifier on the same wafer, capacitively coupled to the 3D readout electronics on top

2. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 2 Recipe: in addition to Tezzaron/Chartered 0.13 µm 2-tiers process from the 3D Consortium (Fermilab, IN2P3, INFN…) use XFAB 0.6 PIN process TSV plus XFAB and Ziptronix (3 tiers) From Chartered (2 tiers) Bonding pads Bumps Wafer view at intermediate and after final stage (chip-to-XFAB wafer bonding)

3. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 3 Chartered Tier_1 (analog) and Tier_2 (digital) XFAB 0.6µm PIN (Tier_0) Ziptronix (Direct Bond Interconnect, DBI®) Shaperless front-end t peak ~1µs Low offset, continuous discriminator Readout logic C d ~ 10 fF C c >100 fF I f >1 nA G x1 C f ~10 fF  off <10 mV D ff ~ 40 µm 2 Q min ~ 200 el 1. Self Triggering Pixel Strip-like Tracker (STriPSeT) Collaboration: Strasbourg-Bergamo-Pavia Tezzaron (metal-metal (Cu) thermocompression)

4. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 4 Principal arguments for use of XFAB-0.6 - fully depleted, 14 µm thick epitaxy - for small pitch, charge contained in less than two pixels - fast charge collection (~5ns)  should be radiation tolerant - sufficient (rather good) S/N ratio defined by the first stage - “charge amplification” ( >x10) by capacitive coupling to the second stage - first experimental results from our first pixel sensor in this process (Mimosa25) very promising! 20x20 µm pixel layout in XFAB-06. Version: SF+CAPA (150 fF)

5. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 5 Mimosa-25 prototypes (XFAB-0.6 PIN, Aug-Dec 2008) 2 submitted chips 20um 4x4 STD 20um 4x4 um STD_TOX 20um 5x6.5 STD 20um 5x6.5 SB 20um 5x6.5 um SB_TOX 20um 5x6.5 um STD_TOX 40um 11.4x11.4 um PIN 30um 4x4 STD 40um 11.4x11.4um STD 40um 5x6.5 um STD 30um 5x6.5 SB 30um 11.4x11.4 PIN Mimosa 25 AMimosa 25 B

6. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 6 To compare: « standard » (non-depleted epi substrate) before and after 10 13 n/cm 2 Landau MP (in electrons) versus cluster size Mimosa-25 on fully depleted epi substrate (XFAB): first tests results (Ru beta) 20 µm pitch, self-bias diode@4.5V before and after neutron irradiation

7. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 7 Mimosa-25 on fully depleted epi substrate : Ru beta spectrum (MIP Landau) seen at the seed pixel, 20 µm pitch, self-bias diode@4.5V 160 e Supposed threshold for ~100% efficiency

8. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 8 Principal arguments for “shaperless front-end” (single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop) - simple (surface efficient) but very satisfactory approach, in particular when minimum signal charge is of few thousand electrons (after “charge amplification”) - shaping time of ~1 µs very convenient: good time resolution, insensitivity to the irradiation induced leakage current - possible implementation of Time-over-Threshold ADC in the future… - minimum signal at the entrance of comparator few tens of mV, so threshold dispersions of few mV tolerable - structure already studied in details by Pavia&Bergamo group (expertise from several prototypes in another 0.13 µm process): minimum risk for this first 3D-3T exercise!

9. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 9 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Two versions of SFE: C f =11 fF (MiM) and 5.5 fF (VPP) Simulation: pulse corresponding to 200 el injected into XFAB diode Results: Peaking time ~400 ns Gain: ~150µV/el (300 µV/el) ENC ~10 electrons! Extra power from SF: <1µW/pixel IF this is correct, we should expect: S/N Landau >40 and Cut 99%eff /Noise>10

10. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 10 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Linearity: 0-4000 electrons (step 100 e)

11. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 11 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Comparator output : 0-4000 electrons (step 100 e); threshold ~150 e

12. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 12 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Time-walk of the comparator output : 0-4000 electrons (step 100 e); thresh ~150 e

13. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 13 Input SuperVias (Input and GND) Self Triggering Pixel Strip-like Tracker: analog pixel (SFE) layout

14. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 14 Principal arguments for “only digital” Tier_2 - excellent separation of analog and digital (no common substrate, several metal layers for blinding…): no problems for asynchronous, random logic - flexibility of the readout architecture, possible use of “front-line”, pure digital CMOS process (<60nm) for this layer to increase complexity of processing at lower power budget

15. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 15 STriPSeT: Data driven (self-triggering), sparsified binary readout. X and Y projection of hit pixels pattern TrigOut Example: readout clock : 160 MHz 2 output lines ≡ Array readout time: ~2µs Programmable Active Area (through pixel disable SR) Readout compatible with existing IPHC-digital DAQ… SR TrigIn DELAY SR Readout or Reset SR: hot pixel disable register

16. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 16 2. Rolling Shutter Mode MAPS: power efficient solution based on M26 approach for processing Collaboration: IRFU-IPHC In-pixel electronics - Common threshold voltage - Only NMOS transistors in Tier 1 - 20x20 µm pitch, 32x256 pixel array - Low power operation (rolling shutter) Example of a power budget: -100 µW/pixel for 50ns processing -To be compared with 500µW/pixel for 200 ns processing (Mimosa26) -Factor of 20 saving in analog power! This is due to 3D electronics…

17. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 17 Tier 1Tier 2 Rolling Shutter Mode MAPS: analog and digital blocks. The analog is based on NMOS transistors only (from Yavuz Degerli) Will be replaced by TSV (SuperContact) in case of 3-Tiers latch diode 20 µm Amplifier chain First stage amplifier

18. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 18 Our contribution to 2009 3D-Consortium submission: one sub- reticle for 3-Tiers CMOS MAPS (plus one for 2-Tiers) Bonding pads 1.8x4 mm Latchup- free Memory (CMP) 3x5.5 mm Small Pitch MAPS for ILC (IPHC) 1.5x5.5 mm Rolling- Shutter MAPS (IRFU) 2-Tiers (2xChartered) 3-Tiers (XFAB+2xChartered) Bonding pads Self-Triggering Pixel Tracker (STriPSeT): 245x245 pixels, 20 µm pitch (Strasbourg-Bergamo-Pavia) 3D3T Test structures and seal rings IRFU-IPHC: rolling-shutter, low power tracker (120x2)x(16+16) pixels, 20x20 (20x10) µm pitch 3D3T Test structures and seal rings Bonding pads

19. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 19 3-Tiers CMOS MAPS status and expected schedule -Submission (Chartered): ~May (done) -Submission (XFAB): ~June/July (building blocks ready) -Reception of wafers: ~August -2 Tiers testing: ~September -XFAB Tier bonding (at Ziptronix): October -Final tests (including beam tests): before the end of 2009? Next steps: 1.Power optimization. In addition to STRipSeT and RSPix, a novel, high-gain (1-2 mV/el), low power (<1µW/pixel) test structure has been submitted 2.Thinning down to ~50 µm. Having such thin wafer, we may propose a new approach to solve yield problems in case of large area devices: built-in redundancy (2complete layers) plus powering off of selected areas after in-situ self-tests 3.Looking for new applications!

20. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 20 Example of application: STriPSeT for the beam telescope -Sensitive area: 5x5 sq.mm  not very large, but fit well Mimosa18 (~1 µm precision tracker) -Expected (binary) resolution: ~5 µm  not very attractive But: -Time resolution of ~300 ns: can accept ~200 kHz particle rate (~10 6 hits/cm 2 s) -Excellent noise performance: cut on S/N ratio of 10 should still be compatible with ~100% efficiency  very low fake counting rate (+ hardware suppression of hot pixels) - Programmable pattern of active area  Good candidate for a (tracking) trigger layer!  Combination of tracking precision and multi-hit capabilities (Mimosa18) plus time resolution (STriPSeT) in one system

21. Wojciech.Dulinski@ires.in2p3.fr 7th Int. Meeting on Front End Electronics, Montauk, May 2009 21 Thanks for your attention! My personal conclusion: a new class of “monolithic” sensors is emerging (Pixel Cube ®?), but the 3-Tiers based architecture is at least 2000 year old! Pont du Gard, southern France