1. 1 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station, TX

2. 2 Outline Background and Motivation Background and Motivation Previous Work Previous Work Simulation Setup Simulation Setup Results and Discussions Results and Discussions Circuit-level hardening guidelines Circuit-level hardening guidelines Model for Charge collected Model for Charge collected Conclusions Conclusions

3. 3 n+n+ S n+n+ p-substrate G D VDD Depletion Region Radiation Particle _ + + _ _ + _ + _ + _ + _ + E _ + VDD - V jn E Charge Deposition by a Radiation Particle Radiation particles - protons, neutrons, alpha particles and heavy ions Radiation particles - protons, neutrons, alpha particles and heavy ions Reverse biased p-n junctions are most sensitive to particle strikes Reverse biased p-n junctions are most sensitive to particle strikes Charge is collected at the drain node through drift and diffusion Charge is collected at the drain node through drift and diffusion Results in a voltage glitch at the drain node Results in a voltage glitch at the drain node System state may change if this voltage glitch is captured by at least one memory element System state may change if this voltage glitch is captured by at least one memory element This is called an SEU This is called an SEU May cause system failure May cause system failure B

4. 4 Radiation Strike Model Charge deposited ( Q D ) by a radiation particle is given by Charge deposited ( Q D ) by a radiation particle is given by where: L is the Linear Energy Transfer (MeV-cm 2 /mg) t is the depth of the collection volume (mm) t is the depth of the collection volume (mm) A radiation particle strike is modeled by a current pulse as A radiation particle strike is modeled by a current pulse as where: Q coll is the amount of charge collected where: Q coll is the amount of charge collected (assumed Q coll = Q D in worst case analysis)   is the collection time constant   is the ion track establishment constant   is the ion track establishment constant The radiation induced current always flows from n -diffusion to p -diffusion The radiation induced current always flows from n -diffusion to p -diffusion Q = 0.1pC   = 150ps   = 50ps

5. 5 Radiation Particle Strikes Radiation particle strike at the output of INV1 Radiation particle strike at the output of INV1 Implemented using 65nm PTM with VDD=1V Implemented using 65nm PTM with VDD=1V Radiation strike: Q =100fC,   =200ps &   =50ps Radiation strike: Q =100fC,   =200ps &   =50ps Models Radiation Particle Strike

6. 6 Motivation Modern VLSI Designs Modern VLSI Designs Vulnerable to noise effects- crosstalk, SEU, etc Vulnerable to noise effects- crosstalk, SEU, etc Single Event Upsets (SEUs) or Soft Errors Single Event Upsets (SEUs) or Soft Errors Troublesome for both memories and combinational logic Troublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial designs Becoming increasingly problematic even for terrestrial designs Applications demand reliable systems Applications demand reliable systems Need to efficiently design radiation tolerant circuits Need to efficiently design radiation tolerant circuits

7. Motivation Power is becoming a major issue Power is becoming a major issue Low power/energy solutions are desired for SoCs, microprocessors, etc Low power/energy solutions are desired for SoCs, microprocessors, etc Both P dyn and P lkg decrease atleast quadratically with decreasing supply voltages Both P dyn and P lkg decrease atleast quadratically with decreasing supply voltages Decrease the supply voltage in the non-critical parts Decrease the supply voltage in the non-critical parts Dynamic voltage scaling (DVS) is extensively used to meet variable speed/power requirements Dynamic voltage scaling (DVS) is extensively used to meet variable speed/power requirements Sub-threshold circuits are also becoming popular to implement extremely low power systems Sub-threshold circuits are also becoming popular to implement extremely low power systems Useful for applications which can tolerate large delay Useful for applications which can tolerate large delay 7

8. 3D Simulations of Radiation Strikes Reliability of DVS and sub-threshold circuits important for the reliability of VLSI systems Reliability of DVS and sub-threshold circuits important for the reliability of VLSI systems Need to analyze the effects of radiation strikes on such circuits Need to analyze the effects of radiation strikes on such circuits Harden the circuits based on the results of this analysis Harden the circuits based on the results of this analysis SPICE cannot be used for this analysis SPICE cannot be used for this analysis The effect of a radiation particle strike is modeled, not the radiation strike itself The effect of a radiation particle strike is modeled, not the radiation strike itself 3D simulations of radiation particle strikes in DVS and sub-threshold circuits need to be performed for an accurate analysis (for example, obtain the fraction of Q D that is collected) 3D simulations of radiation particle strikes in DVS and sub-threshold circuits need to be performed for an accurate analysis (for example, obtain the fraction of Q D that is collected) We performed 3D simulations of a radiation strike in an inverter implemented using a 65 nm technology for different supply voltages (from nominal value to <V T ) We performed 3D simulations of a radiation strike in an inverter implemented using a 65 nm technology for different supply voltages (from nominal value to <V T ) 8

9. Previous Work Palau et al. 2003 studied radiation-induced transients and SER in SRAMs using a 3-D device simulation tool Palau et al. 2003 studied radiation-induced transients and SER in SRAMs using a 3-D device simulation tool Studied effects of different radiation particle tracks on SER Studied effects of different radiation particle tracks on SER Effect of voltage scaling on SER not studied Effect of voltage scaling on SER not studied Irom et al. 2002 performed an experimental study of the effects of radiation strikes in PowerPC microprocessors Irom et al. 2002 performed an experimental study of the effects of radiation strikes in PowerPC microprocessors Processors were implemented using 0.18  m and 0.13  m technologies Processors were implemented using 0.18  m and 0.13  m technologies Reduction of core voltage from 1.6 V to 1.3 V had little effect on SER Reduction of core voltage from 1.6 V to 1.3 V had little effect on SER Flament et al. 2004 experimentally evaluated the sensitivity of various commercial SRAMs to radiation strikes for different supply voltages (VDD) Flament et al. 2004 experimentally evaluated the sensitivity of various commercial SRAMs to radiation strikes for different supply voltages (VDD) SRAMs implemented using technologies ≥ 0.18  m with VDD ≥ 1.5 V SRAMs implemented using technologies ≥ 0.18  m with VDD ≥ 1.5 V 9

10. Previous Work Hazucha et al. 2000 obtained an empirical model for estimation of SER for a 0.6  m CMOS process as a function of the critical charge and VDD through experiments and simulations Hazucha et al. 2000 obtained an empirical model for estimation of SER for a 0.6  m CMOS process as a function of the critical charge and VDD through experiments and simulations A latch with diodes was used for SER measurements for VDD ≥ 2.2V A latch with diodes was used for SER measurements for VDD ≥ 2.2V 3D simulations of a radiation particle strike in diode were performed 3D simulations of a radiation particle strike in diode were performed The above work was conducted in older technologies The above work was conducted in older technologies No circuit level hardening guidelines were proposed No circuit level hardening guidelines were proposed DSM technologies and voltage scaling exhibit different behavior DSM technologies and voltage scaling exhibit different behavior Cannot be used to predict susceptibility of DSM devices at lower VDD Cannot be used to predict susceptibility of DSM devices at lower VDD 10

11. Simulation Setup Implemented in a 65nm bulk technology Implemented in a 65nm bulk technology A radiation particle strike at the drain of the NMOS of INV A radiation particle strike at the drain of the NMOS of INV Simulated using Sentaurus-DEVICE Simulated using Sentaurus-DEVICE Mixed-level device and circuit simulator Mixed-level device and circuit simulator Varied VDD from 0.35V to 1 V Varied VDD from 0.35V to 1 V To simulate sub-threshold and DVS circuits To simulate sub-threshold and DVS circuits |V T | of the PMOS transistor is 0.365V |V T | of the PMOS transistor is 0.365V 3 different INV sizes were simulated 3 different INV sizes were simulated 2X, 4X and 15X 2X, 4X and 15X LET of heavy ions considered are 2, 10 and 20 MeV-cm 2 /mg LET of heavy ions considered are 2, 10 and 20 MeV-cm 2 /mg To simulate low, medium and high energy particle strikes To simulate low, medium and high energy particle strikes Also simulated 4X INV with a radiation strike of LET = 2 & 10 MeV-cm 2 /mg (with different load capacitances) and VDD = 1V Also simulated 4X INV with a radiation strike of LET = 2 & 10 MeV-cm 2 /mg (with different load capacitances) and VDD = 1V To analyze the effect of loading on the radiation susceptibility of the INV To analyze the effect of loading on the radiation susceptibility of the INV 11 in out INV C load Set to GND Radiation Particle 3D Device Model SPICE Model

12. NMOS Device Modeling Constructed NMOS transistors using Sentaurus-Structure editor tool Constructed NMOS transistors using Sentaurus-Structure editor tool Gate length 35nm, T ox = 1.2nm spacer width = 30nm Gate length 35nm, T ox = 1.2nm spacer width = 30nm A heavy ion strikes at the center of the drain A heavy ion strikes at the center of the drain 12 in out1 INV C load 3D Device Model SPICE Model D S G Halo implants V T impant Punch through implant Well Contact Heavy Ion

13. NMOS Device Characterization Characterized the NMOS device using Sentaurus-DEVICE Characterized the NMOS device using Sentaurus-DEVICE Width = 1  m Width = 1  m Good MOSFET characteristics Good MOSFET characteristics 13

14. Results and Discussions Radiation strikes at the output of 4X INV for VDD = 1V Radiation strikes at the output of 4X INV for VDD = 1V Low energy particle is also capable of producing significant voltage glitch Low energy particle is also capable of producing significant voltage glitch For LET = 2 the drain current looks like double exponential For LET = 2 the drain current looks like double exponential Most of the charge gets collected by drift process Most of the charge gets collected by drift process For larger LET values, there is a plateau For larger LET values, there is a plateau Heavily doped substrates demonstrate charge collection due to both drift and diffusion processes– in DSM processes, substrates are heavily doped Heavily doped substrates demonstrate charge collection due to both drift and diffusion processes– in DSM processes, substrates are heavily doped 14

15. Results and Discussions O1 – Small devices collect less charge compared to large devices O1 – Small devices collect less charge compared to large devices Reverse biased electric field is present for shorter duration in small devices Reverse biased electric field is present for shorter duration in small devices Lower drain area – less charge is collected through diffusion Lower drain area – less charge is collected through diffusion G1 – If we upsize a gate to harden it, a higher value of Q coll should be used G1 – If we upsize a gate to harden it, a higher value of Q coll should be used Extremely important for low voltage operation Extremely important for low voltage operation O1.1 – For low energy strikes, Q coll remains roughly constant across different gate sizes for nominal voltage operation O1.1 – For low energy strikes, Q coll remains roughly constant across different gate sizes for nominal voltage operation 15

16. Results and Discussions O2 – For low energy strikes, wide devices collect almost the same amount of charge across different VDD values O2 – For low energy strikes, wide devices collect almost the same amount of charge across different VDD values Reverse biased electric field is present for a long duration Reverse biased electric field is present for a long duration Most of the charge gets collected within a few picoseconds after the strike Most of the charge gets collected within a few picoseconds after the strike G2 – For SPICE simulations and circuit hardening against low energy strikes, it is safe to assume that Q coll remains constant across different VDD values for wide devices G2 – For SPICE simulations and circuit hardening against low energy strikes, it is safe to assume that Q coll remains constant across different VDD values for wide devices O2.1 – Q coll reduces with decreasing VDD O2.1 – Q coll reduces with decreasing VDD At lower VDD, the electric field is weaker than at higher VDD At lower VDD, the electric field is weaker than at higher VDD At higher VDD, the PMOS device is stronger hence, reverse biased electric field is present for a long duration At higher VDD, the PMOS device is stronger hence, reverse biased electric field is present for a long duration 16

17. Results and Discussions O3 – The effect of radiation strikes becomes severe for VDD < 0.6V O3 – The effect of radiation strikes becomes severe for VDD < 0.6V The PMOS which is primarily responsible for recovery becomes weaker at lower VDD values The PMOS which is primarily responsible for recovery becomes weaker at lower VDD values G3 – DVS should scale VDD to 2V T (~60% of nominal value) G3 – DVS should scale VDD to 2V T (~60% of nominal value) A circuit should be hardened at the lowest operating voltage against charge collected at that voltage A circuit should be hardened at the lowest operating voltage against charge collected at that voltage Sub-threshold circuits & circuits with VDD < 2V T need aggressive protection Sub-threshold circuits & circuits with VDD < 2V T need aggressive protection 4X INV, VDD = 1V varying C load 4X INV, VDD = 1V varying C load O4.1 – For medium or high energy strikes, area of voltage glitch increases with increasing C load O4.1 – For medium or high energy strikes, area of voltage glitch increases with increasing C load Voltage glitch magnitude roughly independent of C load Voltage glitch magnitude roughly independent of C load C load ↑ => recovery time ↑ C load ↑ => recovery time ↑ Against common belief Against common belief 17

18. Results and Discussions O4.2 – For low energy strikes, increasing C load improves the radiation tolerance of INV O4.2 – For low energy strikes, increasing C load improves the radiation tolerance of INV Magnitude of the voltage glitch reduces with increasing C load Magnitude of the voltage glitch reduces with increasing C load Difference in magnitude is more for low energy strikes Difference in magnitude is more for low energy strikes PMOS has to recover a lower voltage swing PMOS has to recover a lower voltage swing O4.3 – Q coll increases with increasing C load O4.3 – Q coll increases with increasing C load G4 – C load should be kept low in circuits operating in high energy radiation particle environments G4 – C load should be kept low in circuits operating in high energy radiation particle environments Contrary to conventional wisdom Contrary to conventional wisdom For low energy radiation environments, C load should be kept high For low energy radiation environments, C load should be kept high 18

19. Model for Charge Collected Q coll heavily depends upon VDD, LET and gate size Q coll heavily depends upon VDD, LET and gate size For SPICE level simulations and circuit hardening, worst case Q coll is usually used For SPICE level simulations and circuit hardening, worst case Q coll is usually used May lead to pessimistic designs if this approach is used for hardening DVS circuits May lead to pessimistic designs if this approach is used for hardening DVS circuits Need accurate models for Q coll to improve the accuracy of SPICE simulations Need accurate models for Q coll to improve the accuracy of SPICE simulations We propose one such model We propose one such model K MAX. LET – maximum amount of charge that can be collected. K MAX is obtained from 3D simulations at nominal VDD K MAX. LET – maximum amount of charge that can be collected. K MAX is obtained from 3D simulations at nominal VDD The second term is obtained by curve fitting to the Q coll obtained from 3D simulations The second term is obtained by curve fitting to the Q coll obtained from 3D simulations Parameters of this model be added to SPICE model cards for MOSFETs Parameters of this model be added to SPICE model cards for MOSFETs 19

20. Model for Charge Collected Curve fitting was performed for VDD = 0.6V to 1V Curve fitting was performed for VDD = 0.6V to 1V Applicable to circuits employing DVS Applicable to circuits employing DVS For medium and high energy particle strikes – hardening needs to be performed against such particles For medium and high energy particle strikes – hardening needs to be performed against such particles K MAX = 0.8, K Q = 16.54 fC,  1 = 0.704,  2 = 0.9 and  3 = 0.664 K MAX = 0.8, K Q = 16.54 fC,  1 = 0.704,  2 = 0.9 and  3 = 0.664 Avg. Error is just 6.3% Avg. Error is just 6.3% For low energy strikes, Q coll remains almost constant For low energy strikes, Q coll remains almost constant For sub-threshold circuits, it is difficult to find an accurate model For sub-threshold circuits, it is difficult to find an accurate model Charge collection efficiency is very low Charge collection efficiency is very low 20

21. Conclusions DVS and sub-threshold circuits are increasingly used in VLSI systems DVS and sub-threshold circuits are increasingly used in VLSI systems Important to analyze the effects of radiation particle strikes in these circuits Important to analyze the effects of radiation particle strikes in these circuits Harden the circuits based on this analysis Harden the circuits based on this analysis Performed 3D simulations of a radiation particle strike in an INV with DVS and for sub-threshold operation Performed 3D simulations of a radiation particle strike in an INV with DVS and for sub-threshold operation Made several observations which are important to consider during radiation hardening of these circuits Made several observations which are important to consider during radiation hardening of these circuits Also proposed several guidelines for radiation hardening Also proposed several guidelines for radiation hardening Proposed a model for Q coll to improve accuracy of SPICE simulations – small error of 6.3% Proposed a model for Q coll to improve accuracy of SPICE simulations – small error of 6.3% 21

22. 22 Thank You

23. Backup Slides 23

24. In DSM technologies, a significant amount of charge is collected through diffusion In DSM technologies, a significant amount of charge is collected through diffusion Depends upon the drain-substrate junction area Depends upon the drain-substrate junction area Reduce the drain-substrate junction area Reduce the drain-substrate junction area Share output diffusion node Share output diffusion node Not always possible Not always possible Split one big device into 2 smaller devices and connect them in parallel Split one big device into 2 smaller devices and connect them in parallel Place them a certain distance ( d ) apart from each other Place them a certain distance ( d ) apart from each other When one transistor get struck by a radiation strike, the other collects very little charge When one transistor get struck by a radiation strike, the other collects very little charge Simulated INV of different sizes with the NMOS transistor implemented in this manner Simulated INV of different sizes with the NMOS transistor implemented in this manner D S G S G D S G S G1G1 D S G2G2 S G1G1 D S G2G2 S G2G2 D S G1G1 Layout Guidelines 24 D S G G G d D G1 G2 S

25. Considered vertical and angled strikes – angled towards the second transistor Considered vertical and angled strikes – angled towards the second transistor Vertical strike is the worst case strike for a single device Vertical strike is the worst case strike for a single device Q coll can be reduced by up to 14.5% Q coll can be reduced by up to 14.5% If d is small (< 2  m) then Q coll is higher for angled strikes compared to vertical strikes (not shown) – use single device If d is small (< 2  m) then Q coll is higher for angled strikes compared to vertical strikes (not shown) – use single device Vertical Strike45 o Angled Strike Single Device d (  m) % Red d = 4.2 Single Device d (  m) % Red d = 4.2 2.14.22.14.2 4X LET=1033.230.130.09.7529.630.127.95.74 4X LET=2045.839.339.214.4342.342.137.112.29 8X LET=1053.748.948.59.6545.747.243.54.81 8X LET=2078.167.767.513.5669.471.562.69.80 15X LET=1070.760.960.314.7254.658.753.12.75 15X LET=20123.7109.5108.712.12103.2109.696.56.49 Layout Guidelines 25

26. Standard Cell Layout Guidelines Preference 1 – Reduce the output diffusion area by sharing if possible Preference 1 – Reduce the output diffusion area by sharing if possible Not applicable to devices connected in parallel Not applicable to devices connected in parallel Preference 2 – Split devices, separate them by d ≥ 4  m and connect them in parallel Preference 2 – Split devices, separate them by d ≥ 4  m and connect them in parallel For a 65 nm n-well process For a 65 nm n-well process PMOS devices collect less charge compared to NMOS devices because of lower collection volume PMOS devices collect less charge compared to NMOS devices because of lower collection volume NMOS need to be separated from each other by ≥ 4  m NMOS need to be separated from each other by ≥ 4  m This helps reduce Q coll by 10-14% This helps reduce Q coll by 10-14% 26 N Device P Device n-well N Device P Device n-well VSS VDD VSS N Device P Device n-well 2.6  m VDD VSS