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Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise.

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Presentation on theme: "Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise."— Presentation transcript:

1 Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise

2 Today Inductive Responses –Show math, but let’s not get bogged down in Calculating L Where do inductances show up Impact of inductance on digital circuits How address –Want to make sure we get to last two Penn ESE370 Fall2014 -- DeHon 2

3 Response What happens here? Penn ESE370 Fall2014 -- DeHon 3

4 LC Response Penn ESE370 Fall2014 -- DeHon 4 V2V2

5 LC Response Penn ESE370 Fall2014 -- DeHon 5

6 LC Response Penn ESE370 Fall2014 -- DeHon 6

7 LC Response Penn ESE370 Fall2014 -- DeHon 7

8 LC Response Penn ESE370 Fall2014 -- DeHon 8

9 LC Response Penn ESE370 Fall2014 -- DeHon 9

10 LC Response Penn ESE370 Fall2014 -- DeHon 10

11 LC Response Penn ESE370 Fall2014 -- DeHon 11

12 Response? Penn ESE370 Fall2014 -- DeHon 12

13 RLC Response Penn ESE370 Fall2014 -- DeHon 13 V2V2

14 RLC Response Penn ESE370 Fall2014 -- DeHon 14

15 RLC Response Penn ESE370 Fall2014 -- DeHon 15

16 Solving for w Penn ESE370 Fall2014 -- DeHon 16

17 RLC Penn ESE370 Fall2014 -- DeHon 17

18 RLC Penn ESE370 Fall2014 -- DeHon 18

19 RLC For What happens? –Oscillation Asumming R>0, what else happens? –Decay Penn ESE370 Fall2014 -- DeHon 19

20 DecayOscillation RLC For Penn ESE370 Fall2014 -- DeHon 20

21 RLC Response (R=100) Penn ESE370 Fall2014 -- DeHon 21

22 When Oscillate For what R does this particular circuit oscillate? Penn ESE370 Fall2014 -- DeHon 22

23 RLC Response Penn ESE370 Fall2014 -- DeHon 23

24 Inductance of Wire Penn ESE370 Fall2014 -- DeHon 24

25 Inductance: Wire over Ground Plane Inductance per cm with h=3mil, w=5mil? Penn ESE370 Fall2014 -- DeHon 25

26 Lwire Penn ESE370 Fall2014 -- DeHon 26 C and L per unit length

27 Chip Inductance C wire = 0.16 pF  for the 1mm) C wire = 0.16nF/m Permeability  0 ≈  Si02 =12.6×10 -7 H/m Permitivity  ox =3.5×10 -11 F/m Penn ESE370 Fall2014 -- DeHon 27

28 On Chip C wire = 0.16 pF  for the 1mm) C wire = 0.16nF/m Permeability  0 ≈  Si02 =12.6×10 -7 H/m Permitivity  ox =3.5×10 -11 F/m  pH (for 1 mm) Penn ESE370 Fall2014 -- DeHon 28

29 Comparisons 5mil trace on PCB (preclass 2) Protoboard wires (0.6mm diameter) –About 7nH/cm –http://www.consultrsr.com/resources/eis/induct5.htm On chip wire –0.28nH/mm = 2.8nH/cm Penn ESE370 Fall2014 -- DeHon 29

30 Inductors Bond pads Chip leads Long wire runs Cables Penn ESE370 Fall2014 -- DeHon 30 Src: http://en.wikipedia.org/wiki/File:Wirebonding2.svg

31 Where Arise Penn ESE370 Fall2014 -- DeHon 31

32 Signal Path Penn ESE370 Fall2014 -- DeHon 32

33 Power Ground Penn ESE370 Fall2014 -- DeHon 33

34 Shared Power/Ground Example: 74x04 Penn ESE370 Fall2014 -- DeHon 34

35 Estimate R eq, C eq for gates in parallel –R 0 = 25K  –C 0 = 0.01 fF say 10C 0 =0.1fF for typical load 250 gates switching at clock R eq = 100  C eq =25fF Assume L=1nH How long to settle? Oscillate? Penn ESE370 Fall2014 -- DeHon 35

36 Power Ground Penn ESE370 Fall2014 -- DeHon 36

37 RLC Response Penn ESE370 Fall2014 -- DeHon 37

38 Today’s Chips How many gates? Penn ESE370 Fall2014 -- DeHon 38

39 Multiple Power/Ground Pins Use many power/ground pins How many pins on a package? Divide switching gates by pins –To get effective load on each pin Penn ESE370 Fall2014 -- DeHon 39

40 How Improve Penn ESE370 Fall2014 -- DeHon 40

41 How Improve? Collect thoughts Penn ESE370 Fall2014 -- DeHon 41

42 Minimize the L Make wires short Use power and ground planes –Think of power plane as a very wide wire Impact on C and L? Penn ESE370 Fall2014 -- DeHon 42

43 Flip Chip, Area IO Penn ESE370 Fall2014 -- DeHon 43 www.microwavejournal.com http://www.izm.fraunhofer.de/en/abteilungen/high_density_interconnectwaferlevelpackaging/arbeitsgebiete/arbeitsgebiet1.html

44 Add Good C’s Bypass Capacitors – inside the inductances –On board –On package –On chip Penn ESE370 Fall2014 -- DeHon 44 http://www.legitreviews.com/images/reviews/824/lga_compare.jpg

45 Bypass Capacitor Example Penn ESE370 Fall2014 -- DeHon 45

46 Bypassed Supplies (@ transistor) Penn ESE370 Fall2014 -- DeHon 46

47 Bypassed Output Penn ESE370 Fall2014 -- DeHon 47

48 Minimize Current Draw More Power/Ground Pins Slower rise/fall times Spread out switching Penn ESE370 Fall2014 -- DeHon 48

49 Idea Long wires are inductive –Avoid them –Especially on power supplies Bypass capacitors help Penn ESE370 Fall2014 -- DeHon 49 DecayOscillation

50 Admin Tuesday: Project 2 due Wednesday Lecture –Penn says “Wed. 11/26” is logically a Friday Friday 11/28 is Thanksgiving Holiday Penn ESE370 Fall2014 -- DeHon 50


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