Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary.

Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary Jane Irwin (Penn State)] No Class Tuesday (Veterans Day) Midterms are not graded yet  Grading for Course - Syllabus Doesn’t make sense. It says: Midterm 35% 25% ? Final 25% 30% ? HW 20% 20% ? Projects 20% 25% ? ________________________________________________________________________

Overview of Components and Datapaths Fetch  Decode  Execute  Memory Access  Write Back

MIPS Instruction Times “Stages” Require varying same amount of times: Usually memory access requires the most time. Here, ALU operations are shown as requiring equal time.

Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch Clk Single Cycle Implementation: lwsw Cycle 1Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to stage register overhead What does an R type instruction look like? An immediate?

How Can We Make It Even Faster?  Split the multiple instruction cycle into smaller and smaller steps l There is a point of diminishing returns where as much time is spent loading the state registers as doing the work  Start fetching and executing the next instruction before the current one has completed l Pipelining – (all?) modern processors are pipelined for performance -Remember the performance equation: CPU time = InstructionCount * CyclesPerInstruction * Clock CycleTime  Fetch (and execute) more than one instruction at a time l Superscalar processing, multiple issue machines – stay tuned

A Pipelined MIPS Processor  Start the next instruction before the current one has completed l improves throughput - total amount of work done in a given time l instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5 IFetchDecExecMemWB lw Cycle 7Cycle 6Cycle 8 sw IFetchDecExecMemWB R-type IFetchDecExecMemWB -clock cycle (pipeline stage time) is limited by the slowest stage -for some instructions, some stages are wasted cycles

Single Cycle, Multiple Cycle, Pipeline Multiple Cycle Implementation: Clk Cycle 1 IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch R-type lw IFetchDecExecMemWB Pipeline Implementation: IFetchDecExecMemWB sw IFetchDecExecMemWB R-type Clk Single Cycle Implementation: lwsw Cycle 1Cycle 2

Pipelining the MIPS ISA  What makes it easy? (It’s a RISC architecture) l all instructions are the same length (32 bits) -can fetch in the 1 st stage and decode in the 2 nd stage l few instruction formats (three) with symmetry across formats -can begin reading register file in 2 nd stage l memory operations can occur only in loads and stores -can use the execute stage to calculate memory addresses l each MIPS instruction writes at most one result and does so near the end of the pipeline (MEM and WB)  What makes it difficult? l structural hazards: what if we had only one memory? l control hazards: what about branches? l data hazards: what if an instruction’s input operands depend on the output of a previous instruction?

MIPS Pipeline Datapath Modifications  What do we need to add/modify in our MIPS datapath? l Add State registers between each pipeline stage to isolate them

Graphically Representing MIPS Pipeline  Can help with answering questions like: l How many cycles does it take to execute this code? l What is the ALU doing during cycle 4? l Is there a hazard, why does it occur, and how can it be fixed? ALU IM Reg DMReg

Graphical View of Pipelining I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg Once the pipeline is full, one instruction is completed every cycle, so CPI = 1 Time to “fill” the pipelineTime to “drain” the pipeline

Can Pipelining Get Us Into Trouble?  Yes: Pipeline Hazards l structural hazards: attempt to use the same resource by two different instructions at the same time l data hazards: attempt to use data before it is ready -An instruction’s source operand(s) are produced by a prior instruction still in the pipeline l control hazards: attempt to make a decision about program control flow before the condition has been evaluated and the new PC target address calculated -branch instructions  Can always resolve hazards by waiting l pipeline control must detect the hazard l and take action to resolve hazards

I n s t r. O r d e r Time (clock cycles) lw Inst 1 Inst 2 Inst 4 Inst 3 ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg A Single Memory Would Be a Structural Hazard Reading data from memory Reading instruction from memory  Fix with separate instr and data memories (IM and DM) or better yet, use Dual Port Memory

How About Register File Access? I n s t r. O r d e r Time (clock cycles) add $1, Inst 1 Inst 2 add $2,$1, ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg

How About Register File Access? I n s t r. O r d e r Time (clock cycles) Inst 1 Inst 2 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg Fix register file access hazard by doing reads in the second half of the cycle and writes in the first half add $1, add $2,$1, clock edge that controls register writing clock edge that controls loading of pipeline state registers

Register Usage Can Cause Data Hazards I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  Dependencies backward in time cause hazards  Read before write data hazard

Register Usage Can Cause Data Hazards ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  Dependencies backward in time cause hazards add $1, sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9  Read before write data hazard

Loads Can Cause Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  Dependencies backward in time cause hazards  Load-use data hazard

stall One Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sub $4,$1,$5 and $6,$1,$7 ALU IM Reg DMReg ALU IM Reg DMReg Can fix data hazard by waiting – stall – but impacts CPI

Another Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sub $4,$1,$5 and $6,$1,$7 ALU IM Reg DMReg ALU IM Reg DMReg Fix data hazards by forwarding results as soon as they are available to where they are needed xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DMReg

Another Way to “Fix” a Data Hazard ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg Fix data hazards by forwarding results as soon as they are available to where they are needed ALU IM Reg DMReg ALU IM Reg DMReg I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9

Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg

Forwarding with Load-use Data Hazards ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  Will still need one stall cycle even with forwarding I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9

Branch Instructions Cause Control Hazards I n s t r. O r d e r lw Inst 4 Inst 3 beq ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  Dependencies backward in time cause hazards

stall One Way to “Fix” a Control Hazard I n s t r. O r d e r beq ALU IM Reg DMReg lw ALU IM Reg DMReg ALU Inst 3 IM Reg DM Fix branch hazard by waiting – stall – but affects CPI

We Have a Several Problems to Resolve Yet Write Back Challenge  The Write Back to a register requires that we know the destination register. We have lost that information!  The solution is to carry the destination address (5 bits) forward in the pipeline registers. Control Signal Availability  The Control signals are determined in the Decode stage.  How do we get them to the Stages where they are used?

Corrected Datapath to Save RegWrite Addr  Need to preserve the destination register address in the pipeline state registers

MIPS Pipeline Control Path Modifications  All control signals can be determined during Decode Control

Control Settings EX StageMEM StageWB Stage Reg Dst ALU Op1 ALU Op0 ALU Src BrchMem Read Mem Writ e Reg Writ e Mem toReg R110000010 lw 000101011 sw X0010010X beq X0101000X

Review: MIPS Pipeline Data and Control Paths Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl RegWrite MemWriteMemRead MemtoReg RegDst ALUOp ALUSrc Branch PCSrc

Other Pipeline Structures Are Possible  What about the (slow) multiply operation? l Make the clock twice as slow or … l let it take two cycles (since it doesn’t use the DM stage) ALU IM Reg DMReg MUL ALU IM Reg DM1Reg DM2  What if the data memory access is twice as slow as the instruction memory? l make the clock twice as slow or … l let data memory access take two cycles (and keep the same clock rate) l Probably moot – We probably are using dual port memory

Summary  All modern day processors use pipelining  Pipelining doesn’t help latency of single task, it helps throughput of entire workload  Potential speedup: a CPI of 1 and fast a CC  Pipeline rate limited by slowest pipeline stage l Unbalanced pipe stages makes for inefficiencies l The time to “fill” pipeline and time to “drain” it can impact speedup for deep pipelines and short code runs  Must detect and resolve hazards l Stalling negatively affects CPI (makes CPI higher than the ideal of 1)

Hazards & Inplementation  Pipeline Hazards l structural hazards: attempt to use the same resource by two different instructions at the same time l data hazards: attempt to use data before it is ready -An instruction’s source operand(s) are produced by a prior instruction still in the pipeline l control hazards: attempt to make a decision about program control flow before the condition has been evaluated and the new PC target address calculated -branch instructions  Can always resolve hazards by waiting l pipeline control must detect the hazard l and take action to resolve hazards

stall Recall: One Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sub $4,$1,$5 and $6,$7,$1 ALU IM Reg DMReg ALU IM Reg DMReg Fix data hazard by waiting – stall – but impacts CPI

Recall: Another Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sub $4,$1,$5 and $6,$7,$1 ALU IM Reg DMReg ALU IM Reg DMReg Fix data hazards by forwarding results as soon as they are available to where they are needed sw $4,4($1) or $8,$1,$1 ALU IM Reg DMReg ALU IM Reg DMReg

Data Forwarding (Bypassing Pipeline Registers)  Take the result from the earliest point that it exists in any of the pipeline state registers and forward it to the functional units (e.g., the ALU) that need it that cycle  For ALU functional unit: the inputs can come from any pipeline register rather than just from ID/EX by l adding multiplexors to the inputs of the ALU l connecting the Rd write data in EX/MEM or MEM/WB to either (or both) of the EX’s stage Rs and Rt ALU mux inputs l adding the proper control hardware to control the new muxes  Other functional units may need similar forwarding logic (e.g., the DM)  With forwarding can achieve a CPI of 1 even in the presence of data dependencies

Data Forwarding Control Conditions 1. EX/MEM hazard: if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 Forwards the result from the previous instr. to either input of the ALU Forwards the result from the second previous instr. to either input of the ALU 2. MEM/WB hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Forwarding Illustration I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$7,$1 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg EX/MEM hazard forwarding MEM/WB hazard forwarding

Yet Another Complication! I n s t r. O r d e r add $1,$1,$2 ALU IM Reg DMReg add $1,$1,$3 add $1,$1,$4 ALU IM Reg DMReg ALU IM Reg DMReg  Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded?

Corrected Data Forwarding Control Conditions 2. MEM/WB hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRt) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Datapath with Forwarding Hardware PCSrc Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch Forward Unit

Datapath with Forwarding Hardware PCSrc ID/EX.RegisterRt ID/EX.RegisterRs EX/MEM.RegisterRd MEM/WB.RegisterRd

Memory-to-Memory Copies I n s t r. O r d e r lw $1,4($2) ALU IM Reg DMReg sw $1,4($3) ALU IM Reg DMReg  For loads immediately followed by stores (memory-to- memory copies) can avoid a stall by adding forwarding hardware from the MEM/WB register to the data memory input. l Would need to add a Forward Unit and a mux to the memory access stage

Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DM ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg sub $4,$1,$5

stall Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DM ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9

Load-use Hazard Detection Unit  Need a Hazard detection Unit in the ID stage that inserts a stall between the load and its use 2. ID Hazard Detection if (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))) stall the pipeline  The first line tests to see if the instruction now in the EX stage is a lw ; the next two lines check to see if the destination register of the lw matches either source register of the instruction in the ID stage (the load-use instruction)  After this one cycle stall, the forwarding logic can handle the remaining data hazards

Stall Hardware  Along with the Hazard Unit, we have to implement the stall  Prevent the instructions in the IF and ID stages from progressing down the pipeline – done by preventing the PC register and the IF/ID pipeline register from changing Hazard detection Unit controls the writing of the PC ( PC.write ) and IF/ID ( IF/ID.write ) registers  Insert a “bubble” between the lw instruction (in the EX stage) and the load-use instruction (in the ID stage) (i.e., insert a noop in the execution stream) Set the control bits in the EX, MEM, and WB control fields of the ID/EX pipeline register to 0 ( nop ). The Hazard Unit controls the mux that chooses between the real control values and the 0’s.  Let the lw instruction and the instructions after it in the pipeline (before it in the code) proceed normally down the pipeline

Adding the Hazard Hardware Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch PCSrc Forward Unit Hazard Unit 0 1

Adding the Hazard Hardware Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch PCSrc Forward Unit Hazard Unit 0 1 ID/EX.RegisterRt 0 ID/EX.MemRead

Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary.

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Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary.

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Presentation on theme: "Basic Pipelining & MIPS Pipelining Chapter 6 [Computer Organization and Design, © 2007 Patterson (UCB) & Hennessy (Stanford), & Slides Adapted from: Mary."— Presentation transcript:

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