1. Monitor- ing, Basic IP Header Proc., Packet Classi- fication and Routing APIC Driver Rcv Side APIC Plugin Ctl. Unit... Resource Controller... Rcv Input Side... Rcv Output Side... Packet Scheduler... APIC Driver Xmit Side... Xmit Input Side... Xmit Output Side APIC Register Access Register Access Software Interrupt Level APIC Driver APIC Descs. & AAL5 frame in mbuf data buffers... ip_input tcp/udp_input User Socket Layer Kernel Socket Layer ip_output tcp/udp_output APIC Descs. & AAL5 frame in mbuf data buffers IP Packet in chained mbufs Classified IP Packet in chained mbufs with route IP Packet in chained mbufs APIC Descs. & AAL5 frame in mbuf data buffers Register Access SW Int Cntxt HW Int Cntxt Kernel Space User Space Interrupt IP Opt IP Path Software Interrupt Level APIC Driver User Layer CB Socket Kernel Layer CB Socket Register Access

2. Data Structures: APIC Descriptor Match/Checksum- - BufAddrLo BufAddrHi BufLenNextDesc VISOECLXTY 081624 31 Physical Address of Data Buffer Index into Desc Table Buffer Length or Amount Left Unused O: Read Only, E: EOF, C: CRC OK, T: Type, Y: Valid Bits Buffer Data Byte 0 Byte Buflen - 1 BufAddrLo BufAddrHi

3. Data Structures: mbuf

4. Step 0.1: APIC Driver Initializes Desc. and Buffers Structures 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 Pool X Chain Head 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 MBUF m_data MBUF m_data

5. Step 0.2: APIC Driver Initializes Descriptors and Buffers APIC Driver Rcv Side APIC... Rcv Input Side... Rcv Output Side Register Access APIC Descs. & AAL5 frame in mbuf data buffers Interrupt 0xCAFE- - BufAddrLo = 0 BufAddrHi = 0 0NextDesc = 0 VIS O0O0 E0E0 C0C0 LX T 00 Y 01 VC 101 Queue For each VC that has been opened, the APIC Driver initializes the per VC Current Descriptor register in the APIC hardware to point to a descriptor that is marked DONE_INVALIDLINK. Thus when the APIC starts getting data for this VC, it will be forced to go off and grab the next available Descriptor and re-write the current one with a pointer to the new one. The APIC driver keeps a structure for the VC that keeps a pointer to this chain (our per VC queue!). Y: Valid Bits (01: DONE_INVALIDLINK)

6. Step 0.3: APIC Driver Initializes Descriptors and Buffers APIC Driver Rcv Side APIC... Rcv Input Side... Rcv Output Side Register Access APIC Descs. & AAL5 frame in mbuf data buffers Interrupt 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 Pool X Chain Head 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 MBUF m_data MBUF m_data

7. Step 1: APIC Hardware Writes 3016 byte AAL5 Frame to Memory APIC Driver Rcv Side APIC... Rcv Input Side... Rcv Output Side Register Access APIC Descs. & AAL5 frame in mbuf data buffers Interrupt checksum ???- - BufAddrLo BufAddrHi 0NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 00 checksum- - BufAddrLo BufAddrHi 1016NextDesc ??? VIS O0O0 E1E1 C1C1 LX T 00 Y 00 Pool X Chain Head 0xCAFE- - BufAddrLo BufAddrHi 2016NextDesc VIS O0O0 E0E0 C0C0 LX T 00 Y 11 Need to show how they get linked to the per VC queue that exists. VC 101’ Queue

8. Packet Classi- fication and Routing APIC Driver Rcv Side APIC... Rcv Input Side... Rcv Output Side... Register Access APIC Descs. & AAL5 frame in mbuf data buffers IP Packet in chained mbufs Step 2: APIC Driver Chains Mbufs into IP Packet