1. EE/CS 480/481 111/16/2015 9:02:14 PM University of Portland School of Engineering Project Yew Inline Power Monitor with Cost Analysis Team Zubin Bagai Kevin Eldrige Jon Worley Advisor Dr. Robert Albright Dr. Peter Osterberg Industry Representative Mr. John M. Haner, B.P.A.

2. EE/CS 480/481 2 University of Portland School of Engineering Overview Introduction Functional Diagrams Scorecard Additional Accomplishments Plans Issues/Concerns Conclusions 11/16/2015 9:02:14 PM

3. EE/CS 480/481 3 University of Portland School of Engineering Introduction 11/16/2015 9:02:14 PM Top Level Functional Block Diagram Component Level Block Diagram

4. EE/CS 480/481 4 Power Sensing Functional Diagram 11/16/2015 University of Portland School of Engineering

5. EE/CS 480/481 5 PIC Register Diagram

6. EE/CS 480/481 6 PIC Macro-Model 11/16/2015 University of Portland School of Engineering

7. EE/CS 480/481 7 MOSIS Functional Diagram 11/16/2015 University of Portland School of Engineering

8. EE/CS 480/481 8 CPLD 11/16/2015 University of Portland School of Engineering

9. EE/CS 480/481 911/16/2015 University of Portland School of Engineering Voltage Waveforms

10. EE/CS 480/481 10 University of Portland School of Engineering Scorecard PIC macro-model built Rebuilt sensor circuit Measured voltage from socket through PIC 11/16/2015 9:02:14 PM Completed Shortcomings Voltage Divider circuit gave unexpected values Zubin was out for two weeks CPLD returns unexpected values Relay broke

11. EE/CS 480/481 11 Additional Accomplishments We were able to get accurate A/D conversion from PIC –Sent voltages in, to get binary representations out Got power supply working 11/16/2015 University of Portland School of Engineering

12. EE/CS 480/481 12 University of Portland School of Engineering Plans Finish programming PIC Get our current sensor values in and out of the PIC Complete integration of components Test and debug entire circuit Get and test MOSIS with circuit 11/16/2015 9:02:14 PM

13. EE/CS 480/481 13 University of Portland School of Engineering Milestones 11/16/2015 9:02:14 PM NumberDescriptionOriginal 11 Dec 09 Previous 26 Jan 10 Present 23 Feb 10 19Power Sensor Circuits Built1/26/10 20January Program Review1/26/10 21CPLD Programmed and Tested1/31/101/26/10 22Test Power Sensor with CPLD2/12/10 23PIC Programmed and Tested2/19/10 2/28/10 24February Program Review2/23/10 25System Integration Complete2/26/10 3/5/10 26Finish System Testing with CPLD(s)3/5/10N/A3/5/10 27Spring Break3/8/10N/A3/8/10 28Receive MOSIS Chip and Test in System3/15/10N/A3/15/10 29Implementation of Any Additional Features3/19/10N/A3/19/10 30System Testing Complete3/26/10N/A3/26/10 31March Program Review & Demo3/30/10N/A3/30/10

14. EE/CS 480/481 14 University of Portland School of Engineering Concerns/Issues CPLD clock error Solution: further test bug Backup: Use PIC internal timers System integration was delayed Solution: Schedule more hours each week to catch up 11/16/2015 9:02:14 PM

15. EE/CS 480/481 15 University of Portland School of Engineering Conclusions Project Yew is an Inline Power Monitor Bugs were found but progress was made Plans have been made to catch up Revise voltage measurement System integration is our next target Questions? 11/16/2015 9:02:14 PM