1. George Mason University ECE 449 – Computer Design Lab Introduction to FPGA Devices & Tools

2. George Mason University ECE 449 – Computer Design Lab FPGA Devices

3. 3ECE 449 – Computer Design Lab World of Integrated Circuits Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLDFPGA PALPLAPML LUT (Look-Up Table) MUXGates

4. 4ECE 449 – Computer Design Lab designs must be sent for expensive and time consuming fabrication in semiconductor foundry bought off the shelf and reconfigured by designers themselves Two competing implementation approaches ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array designed all the way from behavioral description to physical layout no physical layout design; design ends with a bitstream used to configure a device

5. 5ECE 449 – Computer Design Lab Block RAMs Configurable Logic Blocks I/O Blocks What is an FPGA? Block RAMs

6. 6ECE 449 – Computer Design Lab Which Way to Go? Off-the-shelf Low development cost Short time to market Reconfigurability High performance ASICsFPGAs Low power Low cost in high volumes

7. 7ECE 449 – Computer Design Lab Other FPGA Advantages Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications reconfigurable computing

8. 8ECE 449 – Computer Design Lab Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp.

9. 9ECE 449 – Computer Design Lab Xilinx  Primary products: FPGAs and the associated CAD software  Main headquarters in San Jose, CA  Fabless* Semiconductor and Software Company  UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}  Seiko Epson (Japan)  TSMC (Taiwan ) Programmable Logic Devices ISE Alliance and Foundation Series Design Software

10. 10ECE 449 – Computer Design Lab Xilinx FPGA Families Old families XC3000, XC4000, XC5200 Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. High-performance families Virtex (0.22µm) Virtex-E, Virtex-EM (0.18µm) Virtex-II, Virtex-II PRO (0.13µm) Low Cost Family Spartan/XL – derived from XC4000 Spartan-II – derived from Virtex Spartan-IIE – derived from Virtex-E Spartan-3

11. 11ECE 449 – Computer Design Lab

12. 12ECE 449 – Computer Design Lab Basic Spartan-II FPGA Block Diagram

13. 13ECE 449 – Computer Design Lab CLB Structure Each slice has 2 LUT-FF pairs with associated carry logic Two 3-state buffers (BUFT) associated with each CLB, accessible by all CLB outputs

14. 14ECE 449 – Computer Design Lab CLB Slice Structure Each slice contains two sets of the following: Four-input LUT Any 4-input logic function, or 16-bit x 1 sync RAM or 16-bit shift register Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

15. 15ECE 449 – Computer Design Lab LUT (Look-Up Table) Functionality Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs

16. 16ECE 449 – Computer Design Lab RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X2S O1 D0 WE WCLK A0 A1 A2 A3 D1 O0 = = LUT or LUT RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 or Distributed RAM CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual- Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read

17. 17ECE 449 – Computer Design Lab DQ CE DQ DQ DQ LUT IN CE CLK DEPTH[3:0] OUT LUT = Shift Register Each LUT can be configured as shift register Serial in, serial out Dynamically addressable delay up to 16 cycles For programmable pipeline Cascade for greater cycle delays Use CLB flip-flops to add depth

18. 18ECE 449 – Computer Design Lab Shift Register Register-rich FPGA Allows for addition of pipeline stages to increase throughput Data paths must be balanced to keep desired functionality 64 Operation A 4 Cycles8 Cycles Operation B 3 Cycles Operation C 64 12 Cycles 3 Cycles 9-Cycle imbalance

19. 19ECE 449 – Computer Design Lab COUT D Q CK S R EC D Q CK R EC O G4 G3 G2 G1 Look-Up Table Carry & Control Logic O YB Y F4 F3 F2 F1 XB X Look-Up Table F5IN BY SR S Carry & Control Logic CIN CLK CE SLICE Carry & Control Logic

20. 20ECE 449 – Computer Design Lab  Each CLB contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters  Carry logic is independent of normal logic and routing resources Fast Carry Logic LSB MSB Carry Logic Routing

21. 21ECE 449 – Computer Design Lab Accessing Carry Logic  All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then…) Counters (count <= count +1)

22. 22ECE 449 – Computer Design Lab Block RAM Spartan-II True Dual-Port Block RAM Port A Port B Block RAM Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements 4 to 14 memory blocks 4096 bits per blocks Use multiple blocks for larger memories Builds both single and true dual-port RAMs

23. 23ECE 449 – Computer Design Lab Spartan-II Block RAM Amounts

24. 24ECE 449 – Computer Design Lab Block RAM Port Aspect Ratios 0 4095 1 1023 4 0 1047 2 0 511 8 0 255 16 0 4k x 1 2k x 2 1k x 4 512 x 8 256 x 16

25. 25ECE 449 – Computer Design Lab Basic I/O Block Structure D EC Q SR D EC Q SR D EC Q SR Three-State Control Output Path Input Path Three-State Output Clock Set/Reset Direct Input Registered Input FF Enable

26. 26ECE 449 – Computer Design Lab IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed

27. 27ECE 449 – Computer Design Lab Routing Resources PSM CLB PSM CLB Programmable Switch Matrix

28. 28ECE 449 – Computer Design Lab Spartan-II FPGA Family Members

29. 29ECE 449 – Computer Design Lab

30. 30ECE 449 – Computer Design Lab Virtex-II 1.5V Architecture C onfigurable L ogic B lock Block RAMs I / O B lock Multipliers 18 x 18 Block RAMs Multipliers 18 x 18 Block RAMs Multipliers 18 x 18 Block RAMs Multipliers 18 x 18

31. 31ECE 449 – Computer Design Lab Virtex-II 1.5V DeviceCLB Array SlicesMaximum I/O BlockRAM (18kb) Multiplier Blocks Distributed RAM bits XC2V408x825688448,192 XC2V8016x85121208816,384 XC2V25024x161,53620024 49,152 XC2V50032x243,07226432 98,304 XC2V100040x325,12043240 163,840 XC2V150048x407,68052848 245,760 XC2V200056x4810,75262456 344,064 XC2V300064x5614,33672096 458,752 XC2V400080x7223,040912120 737,280 XC2V600096x8833,7921,104144 1,081,344 XC2V8000112x10446,5921,108168 1,490,944

32. 32ECE 449 – Computer Design Lab Virtex-II Block SelectRAM Virtex-II BRAM is 18 kbits Additional “parity” bits available in selected configurations WidthDepthAddressDataParity 116,386[13:0][0]N/A 28,192[12:0][1:0]N/A 44,096[11:0][3:0]N/A 92,048[10:0][7:0][0] 181,024[9:0][15:0][1:0] 36512[8:0][31:0][3:0]

33. 33ECE 449 – Computer Design Lab FPGA Nomenclature

34. George Mason University ECE 449 – Computer Design Lab FPGA Tools

35. 35ECE 449 – Computer Design Lab Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

36. 36ECE 449 – Computer Design Lab Design process (2) Implementation Configuration Timing simulation On chip testing

37. 37ECE 449 – Computer Design Lab Design Process control from Active-HDL

38. 38ECE 449 – Computer Design Lab Simulation Tools Many others…

39. 39ECE 449 – Computer Design Lab

40. 40ECE 449 – Computer Design Lab

41. 41ECE 449 – Computer Design Lab Synthesis Tools … and others

42. 42ECE 449 – Computer Design Lab architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

43. 43ECE 449 – Computer Design Lab Features of synthesis tools Interpret RTL code Produce synthesized circuit netlist in a standard EDIF format Give preliminary performance estimates Some can display circuit schematics corresponding to EDIF netlist

44. 44ECE 449 – Computer Design Lab Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

45. 45ECE 449 – Computer Design Lab

46. 46ECE 449 – Computer Design Lab Translation UCF NGD EDIF NCF Native Generic Database file Constraint Editor User Constraint File Native Constraint File Electronic Design Interchange Format Circuit netlistTiming Constraints Synthesis

47. 47ECE 449 – Computer Design Lab Sample UCF File # # Constraints generated by Synplify Pro 7.3.3, Build 039R # # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location Constraints # End of generated constraints NET "clock" LOC = "P88"; NET "control(0)" LOC = "P50"; NET "control(1)" LOC = "P48"; NET "control(2)" LOC = "P42"; NET "reset" LOC = "P93"; NET "segments(0)" LOC = "P67"; NET "segments(1)" LOC = "P39"; NET "segments(2)" LOC = "P62"; NET "segments(3)" LOC = "P60"; NET "segments(4)" LOC = "P46"; NET "segments(5)" LOC = "P57"; NET "segments(6)" LOC = "P49";

48. 48ECE 449 – Computer Design Lab Pin Assignment LAB2 CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) P39 P42 P46 P48 P49 P50 P57 P60 P62 P67 P88 P93 FPGA

49. 49ECE 449 – Computer Design Lab Parallel Port Interface

50. 50ECE 449 – Computer Design Lab Constraints Editor

51. 51ECE 449 – Computer Design Lab Circuit netlist

52. 52ECE 449 – Computer Design Lab Mapping LUT2 LUT3 LUT4 LUT5 LUT1 FF1 FF2

53. 53ECE 449 – Computer Design Lab Placing CLB SLICES FPGA

54. 54ECE 449 – Computer Design Lab Routing Programmable Connections FPGA

55. 55ECE 449 – Computer Design Lab Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency

56. 56ECE 449 – Computer Design Lab Static Timing Analysis Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers DQ in clk DQ out t P logic t Critical = t P FF + t P logic + t S FF

57. 57ECE 449 – Computer Design Lab Static Timing Analysis Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period

58. 58ECE 449 – Computer Design Lab Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

59. 59ECE 449 – Computer Design Lab Resources & Required Reading Spartan FPGA devices Xilinx Spartan-II 2.5V FPGA Family: Complete Data Sheet Module 1: Introduction & Ordering Information Module 2: Functional Description http://direct.xilinx.com/bvdocs/publications/ds001.pdf

60. 60ECE 449 – Computer Design Lab Integrated Interfaces: Active-HDL with Synplify® http://www.aldec.com/Previews/active_synplify.htm Integrated Synthesis and Implementation http://www.aldec.com/Previews/synthesis_implementation.htm Resources & Required Reading FPGA Tools

61. 61ECE 449 – Computer Design Lab Hands-on Session Enough Talking Let’s Get To It !!Brace Yourselves!!

62. 62ECE 449 – Computer Design Lab 0 1 Y [3:0] neg_Y 0 1 ar_log 0 1 2 3 arith [1:0] A + B A - B A <<< 1 A >>> 1 0 1 2 3 logic [1:0] A and B A or B A xor B A xnor B A[3:0] B[3:0] ALU Schematic

63. 63ECE 449 – Computer Design Lab Questions?