1. Digital Integrated Circuit Design
EE141
Digital Integrated Circuit Design
Andrea Bonfanti
DEIB
Via Golgi 40, Milano
Manufacturing Process

2. CMOS Process
n-well CMOS Process

3. Twin-well CMOS Process
Twin-well Trench-Isolated CMOS Process

4. Triple-well CMOS Process

5. Circuit Under Design

6. Its Layout View nwell metal1 n+ diffusion poly p+ diffusion
contact
p+ diffusion

7. Its Layout View (2)

8. Its Layout View (2)

9. Its Layout View (2)

10. Photo-Lithographic Process
optical
mask
oxidation
photoresist
photoresist coating
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
spin, rinse, dry
step

11. Patterning of SiO2 Chemical or plasma etch Si-substrate
Hardened resist
SiO 2
(a) Silicon base material
Si-substrate
Photoresist
SiO 2
(d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2
(b) After oxidation and deposition
Hardened resist
of negative photoresist
SiO 2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO 2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure

12. CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers

13. CMOS Process Walk-Through+
p-epi
(a) Base material: p+ substrate
with p-epi layer p +
p-epi
SiO 2 3 Si N 4
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer) p +
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask

14. CMOS Process Walk-Through
SiO 2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
(e) After n-well and V Tp
adjust implants n
(f) After p-well and V Tn
adjust implants p

15. CMOS Process Walk-Through
(g) After
polysilicon deposition
and etch
poly(silicon)
(h) After n +
source/drain and p
source/drain implants. These
steps also dope the polysilicon.
(i) After deposition of SiO 2
insulator and contact hole etch.
SiO

16. CMOS Process Walk-Through
(j) After deposition and
patterning of first Al layer. Al
(k) After deposition of SiO 2
insulator, etching of via’s,
deposition and patterning of
second layer of Al. Al
SiO

17. Metallization

18. Advanced Metallization

19. Design Rules

20. 3D Perspective
Polysilicon
Aluminum

21. Design Rules Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

22. Single-well CMOS Process Layers
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion (ntap, ptap)
Via
Well (n)
Active (diffuision n+ or p+)
Color
Representation
Yellow
Green
Red
Blue
Magenta
Black
Select (n+)

23. Layers in 0.25 mm CMOS process

24. Intra-Layer Design Rules4
Metal2 3

25. Transistor Layout (PMOS)

26. Vias and Contacts

27. Select Layer

28. CMOS Inverter Layout

29. Layout Editor

30. Design Rule Checker

31. Design Rule Checker

32. The final result

33. Packaging

34. Packaging Requirements
Electrical: low parasitics
Mechanical: reliable and robust
Thermal: efficient heat removal
Economical: cheap

35. Bonding Techniques

36. Tape-Automated Bonding (TAB)

37. Flip-Chip Bonding

38. Package-to-Board Interconnect

39. Package Types

40. Package Parameters

41. Multi-Chip Modules