1. displayCtrlr Specification
Aim: Capture, simulate and implement a multiplexed 7 segment and LED display controller subsystem. Implement on the Digilent Xilinx Spartan-3 FPGA development system. Display four digit values on the 7-segment display element. Assume a 50MHz system clk frequency.
displayCtrlr ISE module VHDL file name is displayCtrlr.vhd
Top (FPGA) level ISE module VHDL file name is d3Design.vhd
The displayCtrlr facilitates hardware debug of FPGA designs implemented during the course
Digilent Spartan-3 Xilinx FPGA hardware development system
displayCtrlr functional partition diagram

2. This document contains:
Contents
This document contains:
Submission / demonstration instructions
Top level FPGA pin connection
Top level d3Design Diagram, Data Dictionary and FPGA pinout
Digilent Spartan-3 development system, 7-segment display circuitry
displayCtrlr Component Incremental Data Dictionary
displayCtrlr process description
Description of ISE project template files provided
Lab instructions
Reference timing diagrams (simulation waveforms)
Expected synthesised RTL schematic

3. Top (FPGA) d3Design Diagram, Data Dictionary and FPGA pinout
clk: system clock strobe
rst: asynchronous reset (H)
btn(2:0): 3 spring loaded switches
sw(7:0): 8 x toggle switches
anL(3:0): 4 x 7-seg display anode control signals (L asserted).
displayCtrlr component asserts (L) one anode control
signal at a time, for a period of 81.92us
seg7L(6:0): 7-seg LEDs, common to each 7-seg
display (L asserted)
dpL: decimal point LED, common to each 7-seg
ld(7:0): 8 x LEDs (H asserted)

4. Digilent Spartan-3 development system, 7-segment display circuitry
7-segent display circuitry

5. Digilent Spartan-3 development system, 7-segment display circuitry
Refer to schematic and User guide (datasheet)

6. displayCtrlr Component Incremental Data Dictionary
dpIn(3:0): 4 x decimal point input values (H asserted)
ldIn(7:0): 8 x LED display data in (H asserted)
seg73Sel(3:0), seg72Sel(3:0), seg71Sel(3:0), seg70Sel(3:0):
digit-wide data for decoding and displaying on 7-seg display
cnt(13:0): 14 bit counter rolls over every 16k (0->16384)*clks
(327.68us).
seg7Sel(1:0): 2-bit combination, changing at 81.92us intervals to enable
practical viewing of data on the 7 segment displays
seg7Sel(1:0) [= cnt(13:12)]
seg7Sel used to generate anL, select 7 segment display
and DP values
data(3:0): digit-wide 7-seg display data input to 7-seg decoder

7. displayCtrlr Process Description
Refer to Digilent Xilinx Spartan 3 h/w development system spec for details on display devices
Pin requirement:
7-segment display data bus (7 pins), anode (4 pins),
decimal point (4 pins). Total = 15 pins
If 7 segment displays are separately hardwired, require
4 x [data bus (7 pins), decimal point (1 pin)]. Total = 32 pins
Counter cnt(13:0) divides system clock (50MHz) to derive slow (81.92us) 2-bit select signals (seg7Sel(1:0))
seg7Sel selects digit display path to 7 segment decoder, DP bit and enables the anode control signals in turn
All 7 segment displays and decimal points are driven with seg7L(6:0) and dpL(3:0) respectively seg7*In are const values selected in turn (using seg7Sel)
LED values display input ld(7:0) values
selDisplay process : selects
digit-wide signal (data) to be decoded in 7 segment decoder (binTo7SegDec)
four anode signals (anL(3:0)) (low asserted)
decimal point signal (dpL) (low asserted)

8. Description of ISE project template files provided
Project file
Simulation user macro (provided) Simulation automatic macro (provided) VHDL Testbench (provided) displayCtrlr synthesisable VHDL model (template code provided, to be completed)
Top (FPGA) level VHDL model (provided)
User constraints file including FPGA pinout assignment
Modelsim preferences file (Provided)
Review all files Project level definitions/components declared in NUIGLibraryPackage/NUIGPackage.vhd

9. Lab instructions
ISE Project : displayCtrlr.ise (provides access to all of the constituent files)
displayCtrlr level VHDL capture and simulation
Complete displayCtrlr.vhd VHDL model template to fully describe the required model. Process labels are included corresponding to the labels on the functional partition
Check VHDL code syntax, synthesise and view RTL schematic.
Review the displayCtrlr VHDL testbench code and Modelsim macro files provided
Simulate fully, review the timing waveform and verify correct VHDL model operation.
d3Design.vhd level
Review and verify the top level design d3Design.vhd model. This includes displayCtrlr component instance connected to the FPGA pins.
Implement on FPGA
Review d3Design.ucf (provided) for pinout
Implement d3Design.vhd top level model and test

10. Timing diagram
Next slide zooms in here

11. Timing diagram
Assert (L) one bit of anL(3:0) at 4096 x clk period intervals anL(3:0) changes from 1110 (E) -> 1101 (D) here

12. Synthesised displayCtrlr symbol
Expected displayCtrlr synthesised (RTL) schematic (for reference)
Synthesised displayCtrlr symbol